From: Andrea Merello <andrea.merello@gmail.com>
To: vkoul@kernel.org, dan.j.williams@intel.com,
michal.simek@xilinx.com, appana.durga.rao@xilinx.com,
dmaengine@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Andrea Merello <andrea.merello@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Subject: [PATCH v3 2/5] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
Date: Mon, 25 Jun 2018 11:27:21 +0200 [thread overview]
Message-ID: <20180625092724.22164-2-andrea.merello@gmail.com> (raw)
In-Reply-To: <20180625092724.22164-1-andrea.merello@gmail.com>
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---
Changes in v2:
- change property name
- property is now optional
- cc DT maintainer
Changes in v3:
- reword
- cc DT maintainerS and ML
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index a2b8bfaec43c..c894abe28baa 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -41,6 +41,7 @@ Optional properties:
- xlnx,include-sg: Tells configured for Scatter-mode in
the hardware.
Optional properties for AXI DMA:
+- xlnx,sg-length-width: Should be the width of the length register as configured in h/w.
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
--
2.17.1
next prev parent reply other threads:[~2018-06-25 9:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-25 9:27 [PATCH v3 1/5] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors Andrea Merello
2018-06-25 9:27 ` Andrea Merello [this message]
2018-06-25 17:29 ` [PATCH v3 2/5] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Rob Herring
2018-06-25 9:27 ` [PATCH v3 3/5] dmaengine: xilinx_dma: program hardware supported buffer length Andrea Merello
2018-06-25 9:27 ` [PATCH v3 4/5] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather Andrea Merello
2018-06-29 7:37 ` Vinod
2018-06-29 7:53 ` Andrea Merello
2018-06-25 9:27 ` [PATCH v3 5/5] dt-bindings: dmaengine: xilinx_dma: drop has-sg property Andrea Merello
2018-06-25 17:30 ` Rob Herring
2018-06-29 7:25 ` [PATCH v3 1/5] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors Vinod
2018-06-29 7:46 ` Andrea Merello
2018-06-29 8:19 ` Vinod
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