From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Wenyou Yang <wenyou.yang@microchip.com>,
Josh Wu <rainyfeeling@outlook.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Marek Vasut <marek.vasut@gmail.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Kamal Dasu <kdasu.kdev@gmail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Han Xu <han.xu@nxp.com>, Harvey Hunt <harveyhuntnexus@gmail.com>,
Vladimir Zapolskiy <vz@mleia.com>,
Sylvain Lemieux <slemieux.tyco@gmail.com>,
Xiaolei Li <xiaolei.li@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Marc Gonzalez <marc.w.gonzalez@free.fr>,
Mans Rullgard <mans@mansr.com>, Stefan Agner <stefan@agner.ch>
Cc: linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com,
linux-mediatek@lists.infradead.org
Subject: [PATCH v4 13/35] mtd: rawnand: marvell: convert driver to nand_scan()
Date: Fri, 20 Jul 2018 17:15:05 +0200 [thread overview]
Message-ID: <20180720151527.16038-14-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20180720151527.16038-1-miquel.raynal@bootlin.com>
Two helpers have been added to the core to make ECC-related
configuration between the detection phase and the final NAND scan. Use
these hooks and convert the driver to just use nand_scan() instead of
both nand_scan_ident() and nand_scan_tail().
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/marvell_nand.c | 205 +++++++++++++++++++-----------------
1 file changed, 108 insertions(+), 97 deletions(-)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index bd5f9a4b7b16..7e5ffef0da76 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -2290,6 +2290,111 @@ static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
return 0;
}
+static int marvell_nand_attach_chip(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
+ struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+ struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev);
+ int ret;
+
+ if (pdata && pdata->flash_bbt)
+ chip->bbt_options |= NAND_BBT_USE_FLASH;
+
+ if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+ /*
+ * We'll use a bad block table stored in-flash and don't
+ * allow writing the bad block marker to the flash.
+ */
+ chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
+ chip->bbt_td = &bbt_main_descr;
+ chip->bbt_md = &bbt_mirror_descr;
+ }
+
+ /* Save the chip-specific fields of NDCR */
+ marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
+ if (chip->options & NAND_BUSWIDTH_16)
+ marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
+
+ /*
+ * On small page NANDs, only one cycle is needed to pass the
+ * column address.
+ */
+ if (mtd->writesize <= 512) {
+ marvell_nand->addr_cyc = 1;
+ } else {
+ marvell_nand->addr_cyc = 2;
+ marvell_nand->ndcr |= NDCR_RA_START;
+ }
+
+ /*
+ * Now add the number of cycles needed to pass the row
+ * address.
+ *
+ * Addressing a chip using CS 2 or 3 should also need the third row
+ * cycle but due to inconsistance in the documentation and lack of
+ * hardware to test this situation, this case is not supported.
+ */
+ if (chip->options & NAND_ROW_ADDR_3)
+ marvell_nand->addr_cyc += 3;
+ else
+ marvell_nand->addr_cyc += 2;
+
+ if (pdata) {
+ chip->ecc.size = pdata->ecc_step_size;
+ chip->ecc.strength = pdata->ecc_strength;
+ }
+
+ ret = marvell_nand_ecc_init(mtd, &chip->ecc);
+ if (ret) {
+ dev_err(nfc->dev, "ECC init failed: %d\n", ret);
+ return ret;
+ }
+
+ if (chip->ecc.mode == NAND_ECC_HW) {
+ /*
+ * Subpage write not available with hardware ECC, prohibit also
+ * subpage read as in userspace subpage access would still be
+ * allowed and subpage write, if used, would lead to numerous
+ * uncorrectable ECC errors.
+ */
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+ }
+
+ if (pdata || nfc->caps->legacy_of_bindings) {
+ /*
+ * We keep the MTD name unchanged to avoid breaking platforms
+ * where the MTD cmdline parser is used and the bootloader
+ * has not been updated to use the new naming scheme.
+ */
+ mtd->name = "pxa3xx_nand-0";
+ } else if (!mtd->name) {
+ /*
+ * If the new bindings are used and the bootloader has not been
+ * updated to pass a new mtdparts parameter on the cmdline, you
+ * should define the following property in your NAND node, ie:
+ *
+ * label = "main-storage";
+ *
+ * This way, mtd->name will be set by the core when
+ * nand_set_flash_node() is called.
+ */
+ mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
+ "%s:nand.%d", dev_name(nfc->dev),
+ marvell_nand->sels[0].cs);
+ if (!mtd->name) {
+ dev_err(nfc->dev, "Failed to allocate mtd->name\n");
+ return -ENOMEM;
+ }
+ }
+
+ return 0;
+}
+
+static const struct nand_controller_ops marvell_nand_controller_ops = {
+ .attach_chip = marvell_nand_attach_chip,
+};
+
static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
struct device_node *np)
{
@@ -2432,105 +2537,11 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
chip->options |= NAND_BUSWIDTH_AUTO;
- ret = nand_scan_ident(mtd, marvell_nand->nsels, NULL);
- if (ret) {
- dev_err(dev, "could not identify the nand chip\n");
- return ret;
- }
-
- if (pdata && pdata->flash_bbt)
- chip->bbt_options |= NAND_BBT_USE_FLASH;
-
- if (chip->bbt_options & NAND_BBT_USE_FLASH) {
- /*
- * We'll use a bad block table stored in-flash and don't
- * allow writing the bad block marker to the flash.
- */
- chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
- chip->bbt_td = &bbt_main_descr;
- chip->bbt_md = &bbt_mirror_descr;
- }
-
- /* Save the chip-specific fields of NDCR */
- marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
- if (chip->options & NAND_BUSWIDTH_16)
- marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
-
- /*
- * On small page NANDs, only one cycle is needed to pass the
- * column address.
- */
- if (mtd->writesize <= 512) {
- marvell_nand->addr_cyc = 1;
- } else {
- marvell_nand->addr_cyc = 2;
- marvell_nand->ndcr |= NDCR_RA_START;
- }
-
- /*
- * Now add the number of cycles needed to pass the row
- * address.
- *
- * Addressing a chip using CS 2 or 3 should also need the third row
- * cycle but due to inconsistance in the documentation and lack of
- * hardware to test this situation, this case is not supported.
- */
- if (chip->options & NAND_ROW_ADDR_3)
- marvell_nand->addr_cyc += 3;
- else
- marvell_nand->addr_cyc += 2;
-
- if (pdata) {
- chip->ecc.size = pdata->ecc_step_size;
- chip->ecc.strength = pdata->ecc_strength;
- }
-
- ret = marvell_nand_ecc_init(mtd, &chip->ecc);
- if (ret) {
- dev_err(dev, "ECC init failed: %d\n", ret);
- return ret;
- }
-
- if (chip->ecc.mode == NAND_ECC_HW) {
- /*
- * Subpage write not available with hardware ECC, prohibit also
- * subpage read as in userspace subpage access would still be
- * allowed and subpage write, if used, would lead to numerous
- * uncorrectable ECC errors.
- */
- chip->options |= NAND_NO_SUBPAGE_WRITE;
- }
-
- if (pdata || nfc->caps->legacy_of_bindings) {
- /*
- * We keep the MTD name unchanged to avoid breaking platforms
- * where the MTD cmdline parser is used and the bootloader
- * has not been updated to use the new naming scheme.
- */
- mtd->name = "pxa3xx_nand-0";
- } else if (!mtd->name) {
- /*
- * If the new bindings are used and the bootloader has not been
- * updated to pass a new mtdparts parameter on the cmdline, you
- * should define the following property in your NAND node, ie:
- *
- * label = "main-storage";
- *
- * This way, mtd->name will be set by the core when
- * nand_set_flash_node() is called.
- */
- mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
- "%s:nand.%d", dev_name(nfc->dev),
- marvell_nand->sels[0].cs);
- if (!mtd->name) {
- dev_err(nfc->dev, "Failed to allocate mtd->name\n");
- return -ENOMEM;
- }
- }
- ret = nand_scan_tail(mtd);
+ chip->controller->ops = &marvell_nand_controller_ops;
+ ret = nand_scan(mtd, marvell_nand->nsels);
if (ret) {
- dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+ dev_err(dev, "could not scan the nand chip\n");
return ret;
}
--
2.14.1
next prev parent reply other threads:[~2018-07-20 15:18 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 15:14 [PATCH v4 00/35] Allow dynamic allocations during NAND chip identification phase Miquel Raynal
2018-07-20 15:14 ` [PATCH v4 01/35] mtd: rawnand: brcmnand: convert driver to nand_scan() Miquel Raynal
2018-07-21 6:23 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 02/35] mtd: rawnand: cafe: " Miquel Raynal
2018-07-21 6:35 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 03/35] mtd: rawnand: davinci: " Miquel Raynal
2018-07-21 6:44 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 04/35] mtd: rawnand: denali: convert " Miquel Raynal
2018-07-21 6:46 ` Boris Brezillon
2018-07-25 9:42 ` Masahiro Yamada
2018-07-25 9:51 ` Boris Brezillon
2018-07-25 12:47 ` Miquel Raynal
2018-07-25 14:16 ` Masahiro Yamada
2018-07-20 15:14 ` [PATCH v4 05/35] mtd: rawnand: fsl_elbc: convert driver " Miquel Raynal
2018-07-21 6:50 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 06/35] mtd: rawnand: fsl_ifc: " Miquel Raynal
2018-07-21 6:53 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 07/35] mtd: rawnand: fsmc: " Miquel Raynal
2018-07-21 6:55 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 08/35] mtd: rawnand: gpmi: " Miquel Raynal
2018-07-21 6:56 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 09/35] mtd: rawnand: hisi504: " Miquel Raynal
2018-07-21 6:59 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 10/35] mtd: rawnand: jz4780: " Miquel Raynal
2018-07-21 15:23 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 11/35] mtd: rawnand: lpc32xx_mlc: " Miquel Raynal
2018-07-21 15:26 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 12/35] mtd: rawnand: lpc32xx_slc: " Miquel Raynal
2018-07-21 15:27 ` Boris Brezillon
2018-07-20 15:15 ` Miquel Raynal [this message]
2018-07-21 16:57 ` [PATCH v4 13/35] mtd: rawnand: marvell: " Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 14/35] mtd: rawnand: mtk: " Miquel Raynal
2018-07-21 17:10 ` Boris Brezillon
2018-07-26 6:06 ` xiaolei li
2018-07-26 6:14 ` Boris Brezillon
2018-07-26 6:46 ` xiaolei li
2018-07-26 6:49 ` Miquel Raynal
2018-07-26 6:53 ` xiaolei li
2018-07-20 15:15 ` [PATCH v4 15/35] mtd: rawnand: mxc: " Miquel Raynal
2018-07-21 17:19 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 16/35] mtd: rawnand: nandsim: " Miquel Raynal
2018-07-21 17:21 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 17/35] mtd: rawnand: omap2: " Miquel Raynal
2018-07-21 17:34 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 18/35] mtd: rawnand: s3c2410: " Miquel Raynal
2018-07-21 17:38 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 19/35] mtd: rawnand: sh_flctl: move all NAND chip related setup in one function Miquel Raynal
2018-07-21 17:48 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 20/35] mtd: rawnand: sh_flctl: convert driver to nand_scan() Miquel Raynal
2018-07-21 17:49 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 21/35] mtd: rawnand: sunxi: " Miquel Raynal
2018-07-21 17:50 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 22/35] mtd: rawnand: tango: " Miquel Raynal
2018-07-21 17:52 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 23/35] mtd: rawnand: txx9ndfmc: rename nand controller internal structure Miquel Raynal
2018-07-21 17:53 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 24/35] mtd: rawnand: txx9ndfmc: convert driver to nand_scan() Miquel Raynal
2018-07-21 17:54 ` Boris Brezillon
2018-07-21 18:04 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 25/35] mtd: rawnand: vf610: " Miquel Raynal
2018-07-21 18:05 ` Boris Brezillon
2018-07-25 8:57 ` Stefan Agner
2018-07-20 15:15 ` [PATCH v4 26/35] mtd: rawnand: atmel: " Miquel Raynal
2018-07-22 6:40 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 27/35] mtd: rawnand: sm_common: convert driver to nand_scan_with_ids() Miquel Raynal
2018-07-22 6:44 ` Boris Brezillon
2018-07-26 19:06 ` Boris Brezillon
2018-07-26 23:13 ` Miquel Raynal
2018-07-20 15:15 ` [PATCH v4 28/35] mtd: rawnand: allow exiting immediately nand_scan_ident() Miquel Raynal
2018-07-22 8:49 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 29/35] mtd: rawnand: docg4: convert driver to nand_scan() Miquel Raynal
2018-07-22 8:52 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 30/35] mtd: rawnand: qcom: " Miquel Raynal
2018-07-22 8:59 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 31/35] mtd: rawnand: jz4740: " Miquel Raynal
2018-07-22 9:29 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 32/35] mtd: rawnand: tegra: " Miquel Raynal
2018-07-22 9:31 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 33/35] mtd: rawnand: do not export nand_scan_[ident|tail]() anymore Miquel Raynal
2018-07-22 10:30 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 34/35] mtd: rawnand: allocate model parameter dynamically Miquel Raynal
2018-07-22 10:32 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 35/35] mtd: rawnand: allocate dynamically ONFI parameters during detection Miquel Raynal
2018-07-22 10:35 ` Boris Brezillon
2018-07-26 23:34 ` [PATCH v4 00/35] Allow dynamic allocations during NAND chip identification phase Miquel Raynal
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