From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Wenyou Yang <wenyou.yang@microchip.com>,
Josh Wu <rainyfeeling@outlook.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Marek Vasut <marek.vasut@gmail.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Kamal Dasu <kdasu.kdev@gmail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Han Xu <han.xu@nxp.com>, Harvey Hunt <harveyhuntnexus@gmail.com>,
Vladimir Zapolskiy <vz@mleia.com>,
Sylvain Lemieux <slemieux.tyco@gmail.com>,
Xiaolei Li <xiaolei.li@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Marc Gonzalez <marc.w.gonzalez@free.fr>,
Mans Rullgard <mans@mansr.com>, Stefan Agner <stefan@agner.ch>
Cc: linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com,
linux-mediatek@lists.infradead.org
Subject: [PATCH v4 03/35] mtd: rawnand: davinci: convert driver to nand_scan()
Date: Fri, 20 Jul 2018 17:14:55 +0200 [thread overview]
Message-ID: <20180720151527.16038-4-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20180720151527.16038-1-miquel.raynal@bootlin.com>
Two helpers have been added to the core to make ECC-related
configuration between the detection phase and the final NAND scan. Use
these hooks and convert the driver to just use nand_scan() instead of
both nand_scan_ident() and nand_scan_tail().
Also change the unused "struct device *dev" parameter of the driver
structure into a platform device to reuse it in the ->attach_chip()
hook.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/davinci_nand.c | 195 +++++++++++++++++++-----------------
1 file changed, 102 insertions(+), 93 deletions(-)
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 626c9363e460..40145e206a6b 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -53,7 +53,7 @@
struct davinci_nand_info {
struct nand_chip chip;
- struct device *dev;
+ struct platform_device *pdev;
bool is_readmode;
@@ -605,6 +605,104 @@ static struct davinci_nand_pdata
}
#endif
+static int davinci_nand_attach_chip(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct davinci_nand_info *info = to_davinci_nand(mtd);
+ struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
+ int ret = 0;
+
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+
+ switch (info->chip.ecc.mode) {
+ case NAND_ECC_NONE:
+ pdata->ecc_bits = 0;
+ break;
+ case NAND_ECC_SOFT:
+ pdata->ecc_bits = 0;
+ /*
+ * This driver expects Hamming based ECC when ecc_mode is set
+ * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
+ * avoid adding an extra ->ecc_algo field to
+ * davinci_nand_pdata.
+ */
+ info->chip.ecc.algo = NAND_ECC_HAMMING;
+ break;
+ case NAND_ECC_HW:
+ if (pdata->ecc_bits == 4) {
+ /*
+ * No sanity checks: CPUs must support this,
+ * and the chips may not use NAND_BUSWIDTH_16.
+ */
+
+ /* No sharing 4-bit hardware between chipselects yet */
+ spin_lock_irq(&davinci_nand_lock);
+ if (ecc4_busy)
+ ret = -EBUSY;
+ else
+ ecc4_busy = true;
+ spin_unlock_irq(&davinci_nand_lock);
+
+ if (ret == -EBUSY)
+ return ret;
+
+ info->chip.ecc.calculate = nand_davinci_calculate_4bit;
+ info->chip.ecc.correct = nand_davinci_correct_4bit;
+ info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
+ info->chip.ecc.bytes = 10;
+ info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
+ info->chip.ecc.algo = NAND_ECC_BCH;
+ } else {
+ /* 1bit ecc hamming */
+ info->chip.ecc.calculate = nand_davinci_calculate_1bit;
+ info->chip.ecc.correct = nand_davinci_correct_1bit;
+ info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
+ info->chip.ecc.bytes = 3;
+ info->chip.ecc.algo = NAND_ECC_HAMMING;
+ }
+ info->chip.ecc.size = 512;
+ info->chip.ecc.strength = pdata->ecc_bits;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Update ECC layout if needed ... for 1-bit HW ECC, the default
+ * is OK, but it allocates 6 bytes when only 3 are needed (for
+ * each 512 bytes). For the 4-bit HW ECC, that default is not
+ * usable: 10 bytes are needed, not 6.
+ */
+ if (pdata->ecc_bits == 4) {
+ int chunks = mtd->writesize / 512;
+
+ if (!chunks || mtd->oobsize < 16) {
+ dev_dbg(&info->pdev->dev, "too small\n");
+ return -EINVAL;
+ }
+
+ /* For small page chips, preserve the manufacturer's
+ * badblock marking data ... and make sure a flash BBT
+ * table marker fits in the free bytes.
+ */
+ if (chunks == 1) {
+ mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
+ } else if (chunks == 4 || chunks == 8) {
+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
+ info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
+ } else {
+ return -EIO;
+ }
+ }
+
+ return ret;
+}
+
+static const struct nand_controller_ops davinci_nand_controller_ops = {
+ .attach_chip = davinci_nand_attach_chip,
+};
+
static int nand_davinci_probe(struct platform_device *pdev)
{
struct davinci_nand_pdata *pdata;
@@ -658,7 +756,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
return -EADDRNOTAVAIL;
}
- info->dev = &pdev->dev;
+ info->pdev = pdev;
info->base = base;
info->vaddr = vaddr;
@@ -708,97 +806,13 @@ static int nand_davinci_probe(struct platform_device *pdev)
spin_unlock_irq(&davinci_nand_lock);
/* Scan to find existence of the device(s) */
- ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
+ info->chip.dummy_controller.ops = &davinci_nand_controller_ops;
+ ret = nand_scan(mtd, pdata->mask_chipsel ? 2 : 1);
if (ret < 0) {
dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
return ret;
}
- switch (info->chip.ecc.mode) {
- case NAND_ECC_NONE:
- pdata->ecc_bits = 0;
- break;
- case NAND_ECC_SOFT:
- pdata->ecc_bits = 0;
- /*
- * This driver expects Hamming based ECC when ecc_mode is set
- * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
- * avoid adding an extra ->ecc_algo field to
- * davinci_nand_pdata.
- */
- info->chip.ecc.algo = NAND_ECC_HAMMING;
- break;
- case NAND_ECC_HW:
- if (pdata->ecc_bits == 4) {
- /* No sanity checks: CPUs must support this,
- * and the chips may not use NAND_BUSWIDTH_16.
- */
-
- /* No sharing 4-bit hardware between chipselects yet */
- spin_lock_irq(&davinci_nand_lock);
- if (ecc4_busy)
- ret = -EBUSY;
- else
- ecc4_busy = true;
- spin_unlock_irq(&davinci_nand_lock);
-
- if (ret == -EBUSY)
- return ret;
-
- info->chip.ecc.calculate = nand_davinci_calculate_4bit;
- info->chip.ecc.correct = nand_davinci_correct_4bit;
- info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
- info->chip.ecc.bytes = 10;
- info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
- info->chip.ecc.algo = NAND_ECC_BCH;
- } else {
- /* 1bit ecc hamming */
- info->chip.ecc.calculate = nand_davinci_calculate_1bit;
- info->chip.ecc.correct = nand_davinci_correct_1bit;
- info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
- info->chip.ecc.bytes = 3;
- info->chip.ecc.algo = NAND_ECC_HAMMING;
- }
- info->chip.ecc.size = 512;
- info->chip.ecc.strength = pdata->ecc_bits;
- break;
- default:
- return -EINVAL;
- }
-
- /* Update ECC layout if needed ... for 1-bit HW ECC, the default
- * is OK, but it allocates 6 bytes when only 3 are needed (for
- * each 512 bytes). For the 4-bit HW ECC, that default is not
- * usable: 10 bytes are needed, not 6.
- */
- if (pdata->ecc_bits == 4) {
- int chunks = mtd->writesize / 512;
-
- if (!chunks || mtd->oobsize < 16) {
- dev_dbg(&pdev->dev, "too small\n");
- ret = -EINVAL;
- goto err;
- }
-
- /* For small page chips, preserve the manufacturer's
- * badblock marking data ... and make sure a flash BBT
- * table marker fits in the free bytes.
- */
- if (chunks == 1) {
- mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
- } else if (chunks == 4 || chunks == 8) {
- mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
- info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
- } else {
- ret = -EIO;
- goto err;
- }
- }
-
- ret = nand_scan_tail(mtd);
- if (ret < 0)
- goto err;
-
if (pdata->parts)
ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
else
@@ -815,11 +829,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
err_cleanup_nand:
nand_cleanup(&info->chip);
-err:
- spin_lock_irq(&davinci_nand_lock);
- if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
- ecc4_busy = false;
- spin_unlock_irq(&davinci_nand_lock);
return ret;
}
--
2.14.1
next prev parent reply other threads:[~2018-07-20 15:15 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 15:14 [PATCH v4 00/35] Allow dynamic allocations during NAND chip identification phase Miquel Raynal
2018-07-20 15:14 ` [PATCH v4 01/35] mtd: rawnand: brcmnand: convert driver to nand_scan() Miquel Raynal
2018-07-21 6:23 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 02/35] mtd: rawnand: cafe: " Miquel Raynal
2018-07-21 6:35 ` Boris Brezillon
2018-07-20 15:14 ` Miquel Raynal [this message]
2018-07-21 6:44 ` [PATCH v4 03/35] mtd: rawnand: davinci: " Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 04/35] mtd: rawnand: denali: convert " Miquel Raynal
2018-07-21 6:46 ` Boris Brezillon
2018-07-25 9:42 ` Masahiro Yamada
2018-07-25 9:51 ` Boris Brezillon
2018-07-25 12:47 ` Miquel Raynal
2018-07-25 14:16 ` Masahiro Yamada
2018-07-20 15:14 ` [PATCH v4 05/35] mtd: rawnand: fsl_elbc: convert driver " Miquel Raynal
2018-07-21 6:50 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 06/35] mtd: rawnand: fsl_ifc: " Miquel Raynal
2018-07-21 6:53 ` Boris Brezillon
2018-07-20 15:14 ` [PATCH v4 07/35] mtd: rawnand: fsmc: " Miquel Raynal
2018-07-21 6:55 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 08/35] mtd: rawnand: gpmi: " Miquel Raynal
2018-07-21 6:56 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 09/35] mtd: rawnand: hisi504: " Miquel Raynal
2018-07-21 6:59 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 10/35] mtd: rawnand: jz4780: " Miquel Raynal
2018-07-21 15:23 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 11/35] mtd: rawnand: lpc32xx_mlc: " Miquel Raynal
2018-07-21 15:26 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 12/35] mtd: rawnand: lpc32xx_slc: " Miquel Raynal
2018-07-21 15:27 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 13/35] mtd: rawnand: marvell: " Miquel Raynal
2018-07-21 16:57 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 14/35] mtd: rawnand: mtk: " Miquel Raynal
2018-07-21 17:10 ` Boris Brezillon
2018-07-26 6:06 ` xiaolei li
2018-07-26 6:14 ` Boris Brezillon
2018-07-26 6:46 ` xiaolei li
2018-07-26 6:49 ` Miquel Raynal
2018-07-26 6:53 ` xiaolei li
2018-07-20 15:15 ` [PATCH v4 15/35] mtd: rawnand: mxc: " Miquel Raynal
2018-07-21 17:19 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 16/35] mtd: rawnand: nandsim: " Miquel Raynal
2018-07-21 17:21 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 17/35] mtd: rawnand: omap2: " Miquel Raynal
2018-07-21 17:34 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 18/35] mtd: rawnand: s3c2410: " Miquel Raynal
2018-07-21 17:38 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 19/35] mtd: rawnand: sh_flctl: move all NAND chip related setup in one function Miquel Raynal
2018-07-21 17:48 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 20/35] mtd: rawnand: sh_flctl: convert driver to nand_scan() Miquel Raynal
2018-07-21 17:49 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 21/35] mtd: rawnand: sunxi: " Miquel Raynal
2018-07-21 17:50 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 22/35] mtd: rawnand: tango: " Miquel Raynal
2018-07-21 17:52 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 23/35] mtd: rawnand: txx9ndfmc: rename nand controller internal structure Miquel Raynal
2018-07-21 17:53 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 24/35] mtd: rawnand: txx9ndfmc: convert driver to nand_scan() Miquel Raynal
2018-07-21 17:54 ` Boris Brezillon
2018-07-21 18:04 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 25/35] mtd: rawnand: vf610: " Miquel Raynal
2018-07-21 18:05 ` Boris Brezillon
2018-07-25 8:57 ` Stefan Agner
2018-07-20 15:15 ` [PATCH v4 26/35] mtd: rawnand: atmel: " Miquel Raynal
2018-07-22 6:40 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 27/35] mtd: rawnand: sm_common: convert driver to nand_scan_with_ids() Miquel Raynal
2018-07-22 6:44 ` Boris Brezillon
2018-07-26 19:06 ` Boris Brezillon
2018-07-26 23:13 ` Miquel Raynal
2018-07-20 15:15 ` [PATCH v4 28/35] mtd: rawnand: allow exiting immediately nand_scan_ident() Miquel Raynal
2018-07-22 8:49 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 29/35] mtd: rawnand: docg4: convert driver to nand_scan() Miquel Raynal
2018-07-22 8:52 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 30/35] mtd: rawnand: qcom: " Miquel Raynal
2018-07-22 8:59 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 31/35] mtd: rawnand: jz4740: " Miquel Raynal
2018-07-22 9:29 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 32/35] mtd: rawnand: tegra: " Miquel Raynal
2018-07-22 9:31 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 33/35] mtd: rawnand: do not export nand_scan_[ident|tail]() anymore Miquel Raynal
2018-07-22 10:30 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 34/35] mtd: rawnand: allocate model parameter dynamically Miquel Raynal
2018-07-22 10:32 ` Boris Brezillon
2018-07-20 15:15 ` [PATCH v4 35/35] mtd: rawnand: allocate dynamically ONFI parameters during detection Miquel Raynal
2018-07-22 10:35 ` Boris Brezillon
2018-07-26 23:34 ` [PATCH v4 00/35] Allow dynamic allocations during NAND chip identification phase Miquel Raynal
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