[PATCH] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[PATCH] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Jacek Tomaka]

From: Jacek Tomaka <jacekt@dugeo.com>

Knights Landing supports half baked LBR_FORMAT_TIME format. The addresses are linear but it does have MISPREDICT bit but nothing else.
Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP. This change teaches LBR about this Knights Landing quirk.
---
 arch/x86/events/intel/lbr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cf372b9055..0f73e60315 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1230,4 +1230,10 @@ void intel_pmu_lbr_init_knl(void)
 
 	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
 	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
+
+	/* Knights Landing supports half baked LBR format. The addresses are linear but it does have MISPREDICT bit.
+	 * Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP.
+	 */
+	if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
+		lbr_desc[LBR_FORMAT_LIP] |= LBR_EIP_FLAGS;
 }
-- 
2.17.0

Re: [PATCH] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Thomas Gleixner]

On Sat, 28 Jul 2018, Jacek Tomaka wrote:

> From: Jacek Tomaka <jacekt@dugeo.com>
> 
> Knights Landing supports half baked LBR_FORMAT_TIME format. The addresses are linear but it does have MISPREDICT bit but nothing else.

I really have no idea what you are trying to explain here.

> Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP. This change teaches LBR about this Knights Landing quirk.

Please use proper line breaks around 78 characters. Also 'This change...'
is equally wrong as 'This patch...'. We know already that this is a
change/patch, right?

See Documentation/process/submitting-patches.rst and search for 'This
patch'.

> ---
>  arch/x86/events/intel/lbr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
> index cf372b9055..0f73e60315 100644
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -1230,4 +1230,10 @@ void intel_pmu_lbr_init_knl(void)
>  
>  	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
>  	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
> +
> +	/* Knights Landing supports half baked LBR format. The addresses are linear but it does have MISPREDICT bit.
> +	 * Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP.
> +	 */

This also wants proper line breaks and please use proper comment style:

       /*
        * This is how a proper multi-line should
	* be formatted.
	*/

> +	if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
> +		lbr_desc[LBR_FORMAT_LIP] |= LBR_EIP_FLAGS;

Thanks,

	tglx