[PATCH v4 0/3] Add support for MSCC Ocelot SPI

[PATCH v4 0/3] Add support for MSCC Ocelot SPI

[Alexandre Belloni]

Hello,

This series only contains the DT documentation and the corresponding DT addition
since it has been rebased on spi-next.

Alexandre Belloni (3):
  spi: dw: document Microsemi integration
  mips: dts: mscc: Add spi on Ocelot
  mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123

 .../devicetree/bindings/spi/snps,dw-apb-ssi.txt       |  6 ++++--
 arch/mips/boot/dts/mscc/ocelot.dtsi                   | 11 +++++++++++
 arch/mips/boot/dts/mscc/ocelot_pcb123.dts             | 10 ++++++++++
 3 files changed, 25 insertions(+), 2 deletions(-)

-- 
2.18.0

[PATCH v4 1/3] spi: dw: document Microsemi integration

[Alexandre Belloni]

The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.

Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
Changes in v4:
 - changed subject to be prefixed by spi: dw:
 - documented possible <soc> values. jaguar2 support will be added later to the
   driver.

 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 204b311e0400..642d3fb1ef85 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,8 +1,10 @@
 Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
 
 Required properties:
-- compatible : "snps,dw-apb-ssi"
-- reg : The register base for the controller.
+- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
+  "jaguar2"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+  register set is required (named ICPU_CFG:SPI_MST)
 - interrupts : One interrupt, used by the controller.
 - #address-cells : <1>, as required by generic SPI binding.
 - #size-cells : <0>, also as required by generic SPI binding.
-- 
2.18.0

[PATCH v4 2/3] mips: dts: mscc: Add spi on Ocelot

[Alexandre Belloni]

Add support for the SPI controller

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 4f33dbc67348..f7616a476247 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -91,6 +91,17 @@
 			status = "disabled";
 		};
 
+		spi: spi@101000 {
+			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x101000 0x100>, <0x3c 0x18>;
+			interrupts = <9>;
+			clocks = <&ahb_clk>;
+
+			status = "disabled";
+		};
+
 		switch@1010000 {
 			compatible = "mscc,vsc7514-switch";
 			reg = <0x1010000 0x10000>,
-- 
2.18.0

[PATCH v4 3/3] mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123

[Alexandre Belloni]

Ocelot PCB123 has a SPI NOR connected on its SPI bus.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 4ccd65379059..2266027759f9 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -26,6 +26,16 @@
 	status = "okay";
 };
 
+&spi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "macronix,mx25l25635f", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
 &mdio0 {
 	status = "okay";
 };
-- 
2.18.0

Applied "spi: dw: document Microsemi integration" to the spi tree

[Mark Brown]

The patch

   spi: dw: document Microsemi integration

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From f09757ab401ff332030f8e3a41cec6a44e6d9461 Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Date: Tue, 31 Jul 2018 16:38:53 +0200
Subject: [PATCH] spi: dw: document Microsemi integration

The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.

Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 204b311e0400..642d3fb1ef85 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,8 +1,10 @@
 Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
 
 Required properties:
-- compatible : "snps,dw-apb-ssi"
-- reg : The register base for the controller.
+- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
+  "jaguar2"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+  register set is required (named ICPU_CFG:SPI_MST)
 - interrupts : One interrupt, used by the controller.
 - #address-cells : <1>, as required by generic SPI binding.
 - #size-cells : <0>, also as required by generic SPI binding.
-- 
2.18.0

Re: [PATCH v4 0/3] Add support for MSCC Ocelot SPI

[Paul Burton]

Hi Alexandre,

On Tue, Jul 31, 2018 at 04:38:52PM +0200, Alexandre Belloni wrote:
> Hello,
> 
> This series only contains the DT documentation and the corresponding DT addition
> since it has been rebased on spi-next.
> 
> Alexandre Belloni (3):
>   spi: dw: document Microsemi integration
>   mips: dts: mscc: Add spi on Ocelot
>   mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
> 
>  .../devicetree/bindings/spi/snps,dw-apb-ssi.txt       |  6 ++++--
>  arch/mips/boot/dts/mscc/ocelot.dtsi                   | 11 +++++++++++
>  arch/mips/boot/dts/mscc/ocelot_pcb123.dts             | 10 ++++++++++
>  3 files changed, 25 insertions(+), 2 deletions(-)

Thanks - looks like the DT binding has been accepted, so I've applied
patches 2 & 3 to mips-next for 4.19.

Paul

Re: [PATCH v4 0/3] Add support for MSCC Ocelot SPI

[Alexandre Belloni]

On 31/07/2018 10:38:09-0700, Paul Burton wrote:
> Hi Alexandre,
> 
> On Tue, Jul 31, 2018 at 04:38:52PM +0200, Alexandre Belloni wrote:
> > Hello,
> > 
> > This series only contains the DT documentation and the corresponding DT addition
> > since it has been rebased on spi-next.
> > 
> > Alexandre Belloni (3):
> >   spi: dw: document Microsemi integration
> >   mips: dts: mscc: Add spi on Ocelot
> >   mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
> > 
> >  .../devicetree/bindings/spi/snps,dw-apb-ssi.txt       |  6 ++++--
> >  arch/mips/boot/dts/mscc/ocelot.dtsi                   | 11 +++++++++++
> >  arch/mips/boot/dts/mscc/ocelot_pcb123.dts             | 10 ++++++++++
> >  3 files changed, 25 insertions(+), 2 deletions(-)
> 
> Thanks - looks like the DT binding has been accepted, so I've applied
> patches 2 & 3 to mips-next for 4.19.
> 

Thank you, it is great to see that going in as this makes the platform
much more useful !


-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com