[PATCH v2 00/10] Add Reset Controller support for Actions Semi Owl SoCs

[PATCH v2 00/10] Add Reset Controller support for Actions Semi Owl SoCs

[Manivannan Sadhasivam]

This patchset adds Reset Controller (RMU) support for Actions Semi
Owl SoCs, S900 and S700. For the Owl SoCs, RMU's registers has been
integrated into the CMU memory map in hardware. Hence, in this patchset
the CMU driver has been converted to syscon so that the same memory map
can be resued by both CMU and RMU drivers. Finally, the support for RMU
in S700 and S900 SoCs are added.

This patch series depends on the recently posted S700 clk series:
"[PATCH v7 0/5] Add clock driver for Actions S700 SoC". For the S700 clk
series, driver and bindings patches are applied through the clk tree.
But the DTS patches are not yet picked up by the platform maintainer,
Andreas.

Hence, Andreas is expected to pick the DTS patches in this series once
reviewed by the maintainers along with S700 clk DTS patches.

Note: I have only tested the S900 part, S700 is only compile tested. But
there is no reason for it to fail.

Thanks,
Mani

Changes in v2:

* Converted the CMU and RMU drivers to syscon for a more cleaner
  approach
* Declared the owl_reset_map structs to const
* Used regmap_update_bits instead of a combined regmap_read and write
* Removed unused headers in RMU drivers
* Added MAINTAINERS entry for the RMU driver and bindings

Manivannan Sadhasivam (10):
  dt-bindings: clock: Add syscon support to Actions Semi Owl SoCs
  arm64: dts: actions: Convert Owl SoCs clock-controller nodes to syscon
  clk: actions: Add syscon support for Actions Semi Owl SoCs
  dt-bindings: reset: Add Actions Semi S900 SoC RMU support
  dt-bindings: reset: Add Actions Semi S700 SoC RMU support
  arm64: dts: actions: Add RMU node for Actions Semi S900 SoC
  arm64: dts: actions: Add RMU node for Actions Semi S700 SoC
  reset: Add Actions Semi S900 SoC Reset Management Unit support
  reset: Add Actions Semi S700 SoC Reset Management Unit support
  MAINTAINERS: Add entry for Actions Semi Owl SoCs Reset Management Unit

 .../bindings/clock/actions,owl-cmu.txt        |  21 +-
 .../bindings/reset/actions,owl-reset.txt      |  35 +++
 MAINTAINERS                                   |   4 +
 arch/arm64/boot/dts/actions/s700.dtsi         |  18 +-
 arch/arm64/boot/dts/actions/s900.dtsi         |  18 +-
 drivers/clk/actions/owl-common.c              |  20 +-
 drivers/reset/Kconfig                         |   6 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-owl.c                     | 225 ++++++++++++++++++
 include/dt-bindings/reset/actions,s700-rmu.h  |  34 +++
 include/dt-bindings/reset/actions,s900-rmu.h  |  65 +++++
 11 files changed, 416 insertions(+), 31 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/actions,owl-reset.txt
 create mode 100644 drivers/reset/reset-owl.c
 create mode 100644 include/dt-bindings/reset/actions,s700-rmu.h
 create mode 100644 include/dt-bindings/reset/actions,s900-rmu.h

-- 
2.17.1

[PATCH v2 01/10] dt-bindings: clock: Add syscon support to Actions Semi Owl SoCs

[Manivannan Sadhasivam]

Since the clock and reset management units are sharing the same memory
map, document the clock bindings to support System Controller.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../bindings/clock/actions,owl-cmu.txt        | 21 +++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
index d1e60d297387..649c95fc4582 100644
--- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
+++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
@@ -9,8 +9,6 @@ Required Properties:
 - compatible: should be one of the following,
 	"actions,s900-cmu"
 	"actions,s700-cmu"
-- reg: physical base address of the controller and length of memory mapped
-  region.
 - clocks: Reference to the parent clocks ("hosc", "losc")
 - #clock-cells: should be 1.
 
@@ -21,6 +19,13 @@ All available clocks are defined as preprocessor macros in corresponding
 dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
 used in device tree sources.
 
+The CMU registers are part of the system-controller block on Owl SoCs.
+
+Parent node should have the following properties :
+- compatible: "syscon", "simple-mfd"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
 External clocks:
 
 The hosc clock used as input for the plls is generated outside the SoC. It is
@@ -31,11 +36,15 @@ Actions Semi S900 CMU also requires one more clock:
 
 Example: Clock Management Unit node:
 
-        cmu: clock-controller@e0160000 {
-                compatible = "actions,s900-cmu";
+        sysctrl: system-controller@e0160000 {
+                compatible = "syscon", "simple-mfd";
                 reg = <0x0 0xe0160000 0x0 0x1000>;
-                clocks = <&hosc>, <&losc>;
-                #clock-cells = <1>;
+
+                cmu: clock-controller {
+                        compatible = "actions,s900-cmu";
+                        clocks = <&hosc>, <&losc>;
+                        #clock-cells = <1>;
+                };
         };
 
 Example: UART controller node that consumes clock generated by the clock
-- 
2.17.1

Re: [PATCH v2 01/10] dt-bindings: clock: Add syscon support to Actions Semi Owl SoCs

[Rob Herring]

On Wed, Aug 01, 2018 at 09:09:06AM +0530, Manivannan Sadhasivam wrote:
> Since the clock and reset management units are sharing the same memory
> map, document the clock bindings to support System Controller.

This is no reason to add child nodes. The existing node can be both a 
clock and reset provider.

> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  .../bindings/clock/actions,owl-cmu.txt        | 21 +++++++++++++------
>  1 file changed, 15 insertions(+), 6 deletions(-)

[PATCH v2 02/10] arm64: dts: actions: Convert Owl SoCs clock-controller nodes to syscon

[Manivannan Sadhasivam]

Since clock and reset management units are sharing the same memory map,
Owl SoCs clock-controller nodes needs to be converted to syscon so that
the corresponding reset drivers can also reuse the same memory region.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/actions/s700.dtsi | 12 ++++++++----
 arch/arm64/boot/dts/actions/s900.dtsi | 12 ++++++++----
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 59d29e4ca404..a57f54587164 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -160,11 +160,15 @@
 			status = "disabled";
 		};
 
-		cmu: clock-controller@e0168000 {
-			compatible = "actions,s700-cmu";
+		sysctrl: system-controller@e0168000 {
+			compatible = "syscon", "simple-mfd";
 			reg = <0x0 0xe0168000 0x0 0x1000>;
-			clocks = <&hosc>, <&losc>;
-			#clock-cells = <1>;
+
+			cmu: clock-controller {
+				compatible = "actions,s700-cmu";
+				clocks = <&hosc>, <&losc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sps: power-controller@e01b0100 {
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index aa3a49b0d646..d239033f9599 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -167,11 +167,15 @@
 			status = "disabled";
 		};
 
-		cmu: clock-controller@e0160000 {
-			compatible = "actions,s900-cmu";
+		sysctrl: system-controller@e0160000 {
+			compatible = "syscon", "simple-mfd";
 			reg = <0x0 0xe0160000 0x0 0x1000>;
-			clocks = <&hosc>, <&losc>;
-			#clock-cells = <1>;
+
+			cmu: clock-controller {
+				compatible = "actions,s900-cmu";
+				clocks = <&hosc>, <&losc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		pinctrl: pinctrl@e01b0000 {
-- 
2.17.1

[PATCH v2 03/10] clk: actions: Add syscon support for Actions Semi Owl SoCs

[Manivannan Sadhasivam]

Since the clock and reset management units are sharing the same memory
map, convert the Owl common clock driver to support System Controller so
that the reset driver can reuse the same memory region.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/clk/actions/owl-common.c | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
index 61c1071b5180..080f980b2ec4 100644
--- a/drivers/clk/actions/owl-common.c
+++ b/drivers/clk/actions/owl-common.c
@@ -8,6 +8,7 @@
 // Copyright (c) 2018 Linaro Ltd.
 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 
+#include <linux/mfd/syscon.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -15,14 +16,6 @@
 
 #include "owl-common.h"
 
-static const struct regmap_config owl_regmap_config = {
-	.reg_bits	= 32,
-	.reg_stride	= 4,
-	.val_bits	= 32,
-	.max_register	= 0x00cc,
-	.fast_io	= true,
-};
-
 static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
 			 struct regmap *regmap)
 {
@@ -41,18 +34,11 @@ static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
 int owl_clk_regmap_init(struct platform_device *pdev,
 			 const struct owl_clk_desc *desc)
 {
-	void __iomem *base;
 	struct regmap *regmap;
-	struct resource *res;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
 
-	regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
+	regmap = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
 	if (IS_ERR(regmap)) {
-		pr_err("failed to init regmap\n");
+		dev_err(&pdev->dev, "failed to get regmap\n");
 		return PTR_ERR(regmap);
 	}
 
-- 
2.17.1

[PATCH v2 04/10] dt-bindings: reset: Add Actions Semi S900 SoC RMU support

[Manivannan Sadhasivam]

Add RMU (Reset Management Unit) support for the Actions Semi S900
SoC which is a part of the Actions Semi Owl family series.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../bindings/reset/actions,owl-reset.txt      | 33 ++++++++++
 include/dt-bindings/reset/actions,s900-rmu.h  | 65 +++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/actions,owl-reset.txt
 create mode 100644 include/dt-bindings/reset/actions,s900-rmu.h

diff --git a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt
new file mode 100644
index 000000000000..38e2c7051d86
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt
@@ -0,0 +1,33 @@
+Actions Semi Owl SoCs Reset Management Unit (RMU)
+=================================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The RMU registers are part of the system-controller block on Owl SoCs.
+
+Required properties:
+- compatible: Should be "actions,s900-rmu"
+- #reset-cells: Should be 1
+
+All available resets are defined as preprocessor macros in corresponding
+dt-bindings/reset/actions,s900-rmu.h header and can be used in device
+tree sources.
+
+Parent node should have the following properties :
+- compatible: "syscon", "simple-mfd"
+- reg: physical base address of the system controller and length of
+  memory mapped region.
+
+Example:
+
+        sysctrl: system-controller@e0160000 {
+                compatible = "syscon", "simple-mfd";
+                reg = <0x0 0xe0160000 0x0 0x1000>;
+
+                rmu: reset-controller {
+                        compatible = "actions,s900-rmu";
+                        #reset-cells = <1>;
+                };
+        };
+
diff --git a/include/dt-bindings/reset/actions,s900-rmu.h b/include/dt-bindings/reset/actions,s900-rmu.h
new file mode 100644
index 000000000000..09e6dca46936
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s900-rmu.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S900 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef _DT_BINDINGS_ACTIONS_S900_RESET_H
+#define _DT_BINDINGS_ACTIONS_S900_RESET_H
+
+#define S900_RESET_CHIPID		0
+#define S900_RESET_CPU_SCNT		1
+#define S900_RESET_SRAMI		2
+#define S900_RESET_DDR_CTL_PHY		3
+#define S900_RESET_DMAC			4
+#define S900_RESET_GPIO			5
+#define S900_RESET_BISP_AXI		6
+#define S900_RESET_CSI0			7
+#define S900_RESET_CSI1			8
+#define S900_RESET_DE			9
+#define S900_RESET_DSI			10
+#define S900_RESET_GPU3D_PA		11
+#define S900_RESET_GPU3D_PB		12
+#define S900_RESET_HDE			13
+#define S900_RESET_I2C0			14
+#define S900_RESET_I2C1			15
+#define S900_RESET_I2C2			16
+#define S900_RESET_I2C3			17
+#define S900_RESET_I2C4			18
+#define S900_RESET_I2C5			19
+#define S900_RESET_IMX			20
+#define S900_RESET_NANDC0		21
+#define S900_RESET_NANDC1		22
+#define S900_RESET_SD0			23
+#define S900_RESET_SD1			24
+#define S900_RESET_SD2			25
+#define S900_RESET_SD3			26
+#define S900_RESET_SPI0			27
+#define S900_RESET_SPI1			28
+#define S900_RESET_SPI2			29
+#define S900_RESET_SPI3			30
+#define S900_RESET_UART0		31
+#define S900_RESET_UART1		32
+#define S900_RESET_UART2		33
+#define S900_RESET_UART3		34
+#define S900_RESET_UART4		35
+#define S900_RESET_UART5		36
+#define S900_RESET_UART6		37
+#define S900_RESET_HDMI			38
+#define S900_RESET_LVDS			39
+#define S900_RESET_EDP			40
+#define S900_RESET_USB2HUB		41
+#define S900_RESET_USB2HSIC		42
+#define S900_RESET_USB3			43
+#define S900_RESET_PCM1			44
+#define S900_RESET_AUDIO		45
+#define S900_RESET_PCM0			46
+#define S900_RESET_SE			47
+#define S900_RESET_GIC			48
+#define S900_RESET_DDR_CTL_PHY_AXI	49
+#define S900_RESET_CMU_DDR		50
+#define S900_RESET_DMM			51
+#define S900_RESET_HDCP2TX		52
+#define S900_RESET_ETHERNET		53
+
+#endif /* _DT_BINDINGS_ACTIONS_S900_RESET_H */
-- 
2.17.1

[PATCH v2 05/10] dt-bindings: reset: Add Actions Semi S700 SoC RMU support

[Manivannan Sadhasivam]

Add RMU (Reset Management Unit) support for the Actions Semi S700
SoC which is a part of the Actions Semi Owl family series.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../bindings/reset/actions,owl-reset.txt      |  8 +++--
 include/dt-bindings/reset/actions,s700-rmu.h  | 34 +++++++++++++++++++
 2 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/reset/actions,s700-rmu.h

diff --git a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt
index 38e2c7051d86..a29950cb2db0 100644
--- a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt
+++ b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt
@@ -7,12 +7,14 @@ controller binding usage.
 The RMU registers are part of the system-controller block on Owl SoCs.
 
 Required properties:
-- compatible: Should be "actions,s900-rmu"
+- compatible: Should be one of the following,
+       "actions,s900-rmu"
+       "actions,s700-rmu"
 - #reset-cells: Should be 1
 
 All available resets are defined as preprocessor macros in corresponding
-dt-bindings/reset/actions,s900-rmu.h header and can be used in device
-tree sources.
+dt-bindings/reset/actions,s900-rmu.h or actions,s700-rmu.h header and can
+be used in device tree sources.
 
 Parent node should have the following properties :
 - compatible: "syscon", "simple-mfd"
diff --git a/include/dt-bindings/reset/actions,s700-rmu.h b/include/dt-bindings/reset/actions,s700-rmu.h
new file mode 100644
index 000000000000..8c5d4d1b8bd4
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s700-rmu.h
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S700 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef _DT_BINDINGS_ACTIONS_S700_RESET_H
+#define _DT_BINDINGS_ACTIONS_S700_RESET_H
+
+#define S700_RESET_AUDIO		0
+#define S700_RESET_CSI			1
+#define S700_RESET_DE			2
+#define S700_RESET_DSI			3
+#define S700_RESET_GPIO			4
+#define S700_RESET_I2C0			5
+#define S700_RESET_I2C1			6
+#define S700_RESET_I2C2			7
+#define S700_RESET_I2C3			8
+#define S700_RESET_KEY			9
+#define S700_RESET_LCD0			10
+#define S700_RESET_SI			11
+#define S700_RESET_SPI0			12
+#define S700_RESET_SPI1			13
+#define S700_RESET_SPI2			14
+#define S700_RESET_SPI3			15
+#define S700_RESET_UART0		16
+#define S700_RESET_UART1		17
+#define S700_RESET_UART2		18
+#define S700_RESET_UART3		19
+#define S700_RESET_UART4		20
+#define S700_RESET_UART5		21
+#define S700_RESET_UART6		22
+
+#endif /* _DT_BINDINGS_ACTIONS_S700_RESET_H */
-- 
2.17.1

[PATCH v2 06/10] arm64: dts: actions: Add RMU node for Actions Semi S900 SoC

[Manivannan Sadhasivam]

Add Reset Controller Unit (RMU) node under the system-controller node
for Actions Semi S900 SoC. Also add the bindings constant header to
be used by clients.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/actions/s900.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index d239033f9599..a242d3193a6a 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/actions,s900-cmu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/actions,s900-rmu.h>
 
 / {
 	compatible = "actions,s900";
@@ -176,6 +177,11 @@
 				clocks = <&hosc>, <&losc>;
 				#clock-cells = <1>;
 			};
+
+			rmu: reset-controller {
+				compatible = "actions,s900-rmu";
+				#reset-cells = <1>;
+			};
 		};
 
 		pinctrl: pinctrl@e01b0000 {
-- 
2.17.1

[PATCH v2 07/10] arm64: dts: actions: Add RMU node for Actions Semi S700 SoC

[Manivannan Sadhasivam]

Add Reset Controller Unit (RMU) node under the system-controller node
for Actions Semi S700 SoC. Also add the bindings constant header to
be used by clients.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/actions/s700.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index a57f54587164..8498579504c7 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/reset/actions,s700-rmu.h>
 
 / {
 	compatible = "actions,s700";
@@ -169,6 +170,11 @@
 				clocks = <&hosc>, <&losc>;
 				#clock-cells = <1>;
 			};
+
+			rmu: reset-controller {
+				compatible = "actions,s700-rmu";
+				#reset-cells = <1>;
+			};
 		};
 
 		sps: power-controller@e01b0100 {
-- 
2.17.1

[PATCH v2 08/10] reset: Add Actions Semi S900 SoC Reset Management Unit support

[Manivannan Sadhasivam]

Add Reset Management Unit (RMU) support for Actions Semi S900 SoC
of the Owl family series. RMU belongs to the Owl SoCs system-controller
which also includes CMU (Clock Management Unit).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/reset/Kconfig     |   6 ++
 drivers/reset/Makefile    |   1 +
 drivers/reset/reset-owl.c | 192 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 199 insertions(+)
 create mode 100644 drivers/reset/reset-owl.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c0b292be1b72..90627430569b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -73,6 +73,12 @@ config RESET_MESON
 	help
 	  This enables the reset driver for Amlogic Meson SoCs.
 
+config RESET_OWL
+	bool "Actions Semi Owl SoCs Reset Driver" if COMPILE_TEST
+	default ARCH_ACTIONS
+	help
+	  This enables the reset controller driver for Actions Semi Owl SoCs.
+
 config RESET_OXNAS
 	bool
 
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c1261dcfe9ad..fa655319cf17 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
+obj-$(CONFIG_RESET_OWL) += reset-owl.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
diff --git a/drivers/reset/reset-owl.c b/drivers/reset/reset-owl.c
new file mode 100644
index 000000000000..c4f07691fb36
--- /dev/null
+++ b/drivers/reset/reset-owl.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+//
+// Actions Semi Owl SoCs Reset Management Unit driver
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/actions,s900-rmu.h>
+
+#define CMU_DEVRST0 0x00a8
+#define CMU_DEVRST1 0x00ac
+
+struct owl_reset_map {
+	u32	reg;
+	u32	bit;
+};
+
+struct owl_reset_hw {
+	const struct owl_reset_map *resets;
+	u32 num_resets;
+};
+
+struct owl_reset {
+	struct reset_controller_dev	rcdev;
+	const struct owl_reset_hw	*hw;
+	struct regmap			*regmap;
+};
+
+static const struct owl_reset_map s900_resets[] = {
+	[S900_RESET_DMAC]		= { CMU_DEVRST0, BIT(0) },
+	[S900_RESET_SRAMI]		= { CMU_DEVRST0, BIT(1) },
+	[S900_RESET_DDR_CTL_PHY]	= { CMU_DEVRST0, BIT(2) },
+	[S900_RESET_NANDC0]		= { CMU_DEVRST0, BIT(3) },
+	[S900_RESET_SD0]		= { CMU_DEVRST0, BIT(4) },
+	[S900_RESET_SD1]		= { CMU_DEVRST0, BIT(5) },
+	[S900_RESET_PCM1]		= { CMU_DEVRST0, BIT(6) },
+	[S900_RESET_DE]			= { CMU_DEVRST0, BIT(7) },
+	[S900_RESET_LVDS]		= { CMU_DEVRST0, BIT(8) },
+	[S900_RESET_SD2]		= { CMU_DEVRST0, BIT(9) },
+	[S900_RESET_DSI]		= { CMU_DEVRST0, BIT(10) },
+	[S900_RESET_CSI0]		= { CMU_DEVRST0, BIT(11) },
+	[S900_RESET_BISP_AXI]		= { CMU_DEVRST0, BIT(12) },
+	[S900_RESET_CSI1]		= { CMU_DEVRST0, BIT(13) },
+	[S900_RESET_GPIO]		= { CMU_DEVRST0, BIT(15) },
+	[S900_RESET_EDP]		= { CMU_DEVRST0, BIT(16) },
+	[S900_RESET_AUDIO]		= { CMU_DEVRST0, BIT(17) },
+	[S900_RESET_PCM0]		= { CMU_DEVRST0, BIT(18) },
+	[S900_RESET_HDE]		= { CMU_DEVRST0, BIT(21) },
+	[S900_RESET_GPU3D_PA]		= { CMU_DEVRST0, BIT(22) },
+	[S900_RESET_IMX]		= { CMU_DEVRST0, BIT(23) },
+	[S900_RESET_SE]			= { CMU_DEVRST0, BIT(24) },
+	[S900_RESET_NANDC1]		= { CMU_DEVRST0, BIT(25) },
+	[S900_RESET_SD3]		= { CMU_DEVRST0, BIT(26) },
+	[S900_RESET_GIC]		= { CMU_DEVRST0, BIT(27) },
+	[S900_RESET_GPU3D_PB]		= { CMU_DEVRST0, BIT(28) },
+	[S900_RESET_DDR_CTL_PHY_AXI]	= { CMU_DEVRST0, BIT(29) },
+	[S900_RESET_CMU_DDR]		= { CMU_DEVRST0, BIT(30) },
+	[S900_RESET_DMM]		= { CMU_DEVRST0, BIT(31) },
+	[S900_RESET_USB2HUB]		= { CMU_DEVRST1, BIT(0) },
+	[S900_RESET_USB2HSIC]		= { CMU_DEVRST1, BIT(1) },
+	[S900_RESET_HDMI]		= { CMU_DEVRST1, BIT(2) },
+	[S900_RESET_HDCP2TX]		= { CMU_DEVRST1, BIT(3) },
+	[S900_RESET_UART6]		= { CMU_DEVRST1, BIT(4) },
+	[S900_RESET_UART0]		= { CMU_DEVRST1, BIT(5) },
+	[S900_RESET_UART1]		= { CMU_DEVRST1, BIT(6) },
+	[S900_RESET_UART2]		= { CMU_DEVRST1, BIT(7) },
+	[S900_RESET_SPI0]		= { CMU_DEVRST1, BIT(8) },
+	[S900_RESET_SPI1]		= { CMU_DEVRST1, BIT(9) },
+	[S900_RESET_SPI2]		= { CMU_DEVRST1, BIT(10) },
+	[S900_RESET_SPI3]		= { CMU_DEVRST1, BIT(11) },
+	[S900_RESET_I2C0]		= { CMU_DEVRST1, BIT(12) },
+	[S900_RESET_I2C1]		= { CMU_DEVRST1, BIT(13) },
+	[S900_RESET_USB3]		= { CMU_DEVRST1, BIT(14) },
+	[S900_RESET_UART3]		= { CMU_DEVRST1, BIT(15) },
+	[S900_RESET_UART4]		= { CMU_DEVRST1, BIT(16) },
+	[S900_RESET_UART5]		= { CMU_DEVRST1, BIT(17) },
+	[S900_RESET_I2C2]		= { CMU_DEVRST1, BIT(18) },
+	[S900_RESET_I2C3]		= { CMU_DEVRST1, BIT(19) },
+};
+
+static const struct owl_reset_hw s900_reset_hw = {
+	.resets = s900_resets,
+	.num_resets = ARRAY_SIZE(s900_resets),
+};
+
+static inline struct owl_reset *to_owl_reset(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct owl_reset, rcdev);
+}
+
+static int owl_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	struct owl_reset *reset = to_owl_reset(rcdev);
+	const struct owl_reset_map *map = &reset->hw->resets[id];
+
+	return regmap_update_bits(reset->regmap, map->reg, map->bit, 0);
+}
+
+static int owl_reset_deassert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct owl_reset *reset = to_owl_reset(rcdev);
+	const struct owl_reset_map *map = &reset->hw->resets[id];
+
+	return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit);
+}
+
+static int owl_reset_reset(struct reset_controller_dev *rcdev,
+			   unsigned long id)
+{
+	owl_reset_assert(rcdev, id);
+	udelay(1);
+	owl_reset_deassert(rcdev, id);
+
+	return 0;
+}
+
+static int owl_reset_status(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	struct owl_reset *reset = to_owl_reset(rcdev);
+	const struct owl_reset_map *map = &reset->hw->resets[id];
+	u32 reg;
+	int ret;
+
+	ret = regmap_read(reset->regmap, map->reg, &reg);
+	if (ret)
+		return ret;
+
+	/*
+	 * The reset control API expects 0 if reset is not asserted,
+	 * which is the opposite of what our hardware uses.
+	 */
+	return !(map->bit & reg);
+}
+
+static const struct reset_control_ops owl_reset_ops = {
+	.assert         = owl_reset_assert,
+	.deassert       = owl_reset_deassert,
+	.reset          = owl_reset_reset,
+	.status         = owl_reset_status,
+};
+
+static int owl_reset_probe(struct platform_device *pdev)
+{
+	struct owl_reset *reset;
+	struct regmap *regmap;
+	const struct owl_reset_hw *hw;
+
+	hw = of_device_get_match_data(&pdev->dev);
+	if (!hw)
+		return -EINVAL;
+
+	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+	if (!reset)
+		return -ENOMEM;
+
+	regmap = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
+	if (IS_ERR(regmap)) {
+		dev_err(&pdev->dev, "failed to get regmap\n");
+		return PTR_ERR(regmap);
+	}
+
+	reset->rcdev.of_node = pdev->dev.of_node;
+	reset->rcdev.ops = &owl_reset_ops;
+	reset->rcdev.nr_resets = hw->num_resets;
+	reset->hw = hw;
+	reset->regmap = regmap;
+
+	return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+}
+
+static const struct of_device_id owl_reset_of_match[] = {
+	{ .compatible = "actions,s900-rmu", .data = &s900_reset_hw },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver owl_reset_driver = {
+	.probe = owl_reset_probe,
+	.driver = {
+		.name = "owl-reset",
+		.of_match_table = owl_reset_of_match,
+	},
+};
+builtin_platform_driver(owl_reset_driver);
-- 
2.17.1

[PATCH v2 09/10] reset: Add Actions Semi S700 SoC Reset Management Unit support

[Manivannan Sadhasivam]

Add Reset Management Unit (RMU) support for Actions Semi S700 SoC
of the Owl family series. RMU belongs to the Owl SoCs system-controller
which also includes CMU (Clock Management Unit).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/reset/reset-owl.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/reset/reset-owl.c b/drivers/reset/reset-owl.c
index c4f07691fb36..2e761c64f81b 100644
--- a/drivers/reset/reset-owl.c
+++ b/drivers/reset/reset-owl.c
@@ -12,6 +12,7 @@
 #include <linux/reset-controller.h>
 
 #include <dt-bindings/reset/actions,s900-rmu.h>
+#include <dt-bindings/reset/actions,s700-rmu.h>
 
 #define CMU_DEVRST0 0x00a8
 #define CMU_DEVRST1 0x00ac
@@ -84,11 +85,42 @@ static const struct owl_reset_map s900_resets[] = {
 	[S900_RESET_I2C3]		= { CMU_DEVRST1, BIT(19) },
 };
 
+static const struct owl_reset_map s700_resets[] = {
+	[S700_RESET_DE]      = { CMU_DEVRST0, BIT(0) },
+	[S700_RESET_LCD0]    = { CMU_DEVRST0, BIT(1) },
+	[S700_RESET_DSI]     = { CMU_DEVRST0, BIT(2) },
+	[S700_RESET_CSI]     = { CMU_DEVRST0, BIT(13) },
+	[S700_RESET_SI]      = { CMU_DEVRST0, BIT(14) },
+	[S700_RESET_I2C0]    = { CMU_DEVRST1, BIT(0) },
+	[S700_RESET_I2C1]    = { CMU_DEVRST1, BIT(1) },
+	[S700_RESET_I2C2]    = { CMU_DEVRST1, BIT(2) },
+	[S700_RESET_I2C3]    = { CMU_DEVRST1, BIT(3) },
+	[S700_RESET_SPI0]    = { CMU_DEVRST1, BIT(4) },
+	[S700_RESET_SPI1]    = { CMU_DEVRST1, BIT(5) },
+	[S700_RESET_SPI2]    = { CMU_DEVRST1, BIT(6) },
+	[S700_RESET_SPI3]    = { CMU_DEVRST1, BIT(7) },
+	[S700_RESET_UART0]   = { CMU_DEVRST1, BIT(8) },
+	[S700_RESET_UART1]   = { CMU_DEVRST1, BIT(9) },
+	[S700_RESET_UART2]   = { CMU_DEVRST1, BIT(10) },
+	[S700_RESET_UART3]   = { CMU_DEVRST1, BIT(11) },
+	[S700_RESET_UART4]   = { CMU_DEVRST1, BIT(12) },
+	[S700_RESET_UART5]   = { CMU_DEVRST1, BIT(13) },
+	[S700_RESET_UART6]   = { CMU_DEVRST1, BIT(14) },
+	[S700_RESET_KEY]     = { CMU_DEVRST1, BIT(24) },
+	[S700_RESET_GPIO]    = { CMU_DEVRST1, BIT(25) },
+	[S700_RESET_AUDIO]   = { CMU_DEVRST1, BIT(29) },
+};
+
 static const struct owl_reset_hw s900_reset_hw = {
 	.resets = s900_resets,
 	.num_resets = ARRAY_SIZE(s900_resets),
 };
 
+static const struct owl_reset_hw s700_reset_hw = {
+	.resets = s700_resets,
+	.num_resets = ARRAY_SIZE(s700_resets),
+};
+
 static inline struct owl_reset *to_owl_reset(struct reset_controller_dev *rcdev)
 {
 	return container_of(rcdev, struct owl_reset, rcdev);
@@ -179,6 +211,7 @@ static int owl_reset_probe(struct platform_device *pdev)
 
 static const struct of_device_id owl_reset_of_match[] = {
 	{ .compatible = "actions,s900-rmu", .data = &s900_reset_hw },
+	{ .compatible = "actions,s700-rmu", .data = &s700_reset_hw },
 	{ /* sentinel */ }
 };
 
-- 
2.17.1

[PATCH v2 10/10] MAINTAINERS: Add entry for Actions Semi Owl SoCs Reset Management Unit

[Manivannan Sadhasivam]

Add entry for Actions Semi Reset Management Unit driver and its
bindings under ARCH_ACTIONS. Currently only S700 and S900 SoCs
of the Owl family are supported.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 MAINTAINERS | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9c292ef3c210..25934ae77ba6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1146,13 +1146,17 @@ F:	arch/arm64/boot/dts/actions/
 F:	drivers/clk/actions/
 F:	drivers/clocksource/owl-*
 F:	drivers/pinctrl/actions/*
+F:	drivers/reset/reset-owl.c
 F:	drivers/soc/actions/
 F:	include/dt-bindings/power/owl-*
+F:	include/dt-bindings/reset/actions,s700-rmu.h
+F:	include/dt-bindings/reset/actions,s900-rmu.h
 F:	include/linux/soc/actions/
 F:	Documentation/devicetree/bindings/arm/actions.txt
 F:	Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
 F:	Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
 F:	Documentation/devicetree/bindings/power/actions,owl-sps.txt
+F:	Documentation/devicetree/bindings/reset/actions,owl-reset.txt
 F:	Documentation/devicetree/bindings/timer/actions,owl-timer.txt
 
 ARM/ADS SPHERE MACHINE SUPPORT
-- 
2.17.1