From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: tglx@linutronix.de, mingo@redhat.com, acme@kernel.org,
linux-kernel@vger.kernel.org, eranian@google.com,
ak@linux.intel.com, alexander.shishkin@linux.intel.com
Subject: Re: [PATCH 2/3] x86, perf: Add a separate Arch Perfmon v4 PMI handler
Date: Tue, 7 Aug 2018 19:31:37 +0200 [thread overview]
Message-ID: <20180807173137.GG2494@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <fb5eb1f8-f071-d9e5-2ee3-372aa8f64525@linux.intel.com>
On Tue, Aug 07, 2018 at 11:29:54AM -0400, Liang, Kan wrote:
> On 8/6/2018 2:35 PM, Peter Zijlstra wrote:
> > On Mon, Aug 06, 2018 at 10:23:42AM -0700, kan.liang@linux.intel.com wrote:
> > > @@ -2044,6 +2056,14 @@ static void intel_pmu_disable_event(struct perf_event *event)
> > > if (unlikely(event->attr.precise_ip))
> > > intel_pmu_pebs_disable(event);
> > > + /*
> > > + * We could disable freezing here, but doesn't hurt if it's on.
> > > + * perf remembers the state, and someone else will likely
> > > + * reinitialize.
> > > + *
> > > + * This avoids an extra MSR write in many situations.
> > > + */
> > > +
> > > if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
> > > intel_pmu_disable_fixed(hwc);
> > > return;
> > > @@ -2119,6 +2139,11 @@ static void intel_pmu_enable_event(struct perf_event *event)
> > > if (event->attr.exclude_guest)
> > > cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
> > > + if (x86_pmu.counter_freezing && !cpuc->frozen_enabled) {
> > > + enable_counter_freeze();
> > > + cpuc->frozen_enabled = 1;
> > > + }
> > > +
> > > if (unlikely(event_is_checkpointed(event)))
> > > cpuc->intel_cp_status |= (1ull << hwc->idx);
> >
> > Why here? That doesn't really make sense; should this not be in
> > intel_pmu_cpu_starting() or something?
>
>
> For Goldmont Plus, the counter freezing feature can be re-enabled at
> run-time by loading a newer microcode.
> We need to check the x86_pmu.counter_freezing every time.
Blergh, just don't go there. If we start with the wrong ucode, leave it
disabled.
We do that for most ucode stuff.
next prev parent reply other threads:[~2018-08-07 17:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-06 17:23 [PATCH 1/3] perf/x86/intel: Factor out common code of PMI handler kan.liang
2018-08-06 17:23 ` [PATCH 2/3] x86, perf: Add a separate Arch Perfmon v4 " kan.liang
2018-08-06 18:35 ` Peter Zijlstra
2018-08-06 21:33 ` Andi Kleen
2018-08-06 21:50 ` Peter Zijlstra
2018-08-07 15:29 ` Liang, Kan
2018-08-07 17:31 ` Peter Zijlstra [this message]
2018-08-06 17:23 ` [PATCH 3/3] perf/x86/intel: Add quirk for Goldmont Plus kan.liang
2018-08-06 18:39 ` Peter Zijlstra
2018-08-07 15:30 ` Liang, Kan
2018-08-06 18:20 ` [PATCH 1/3] perf/x86/intel: Factor out common code of PMI handler Peter Zijlstra
2018-08-07 15:29 ` Liang, Kan
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