From: Thierry Reding <thierry.reding@gmail.com>
To: Aapo Vienamo <avienamo@nvidia.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration
Date: Thu, 9 Aug 2018 13:48:05 +0200 [thread overview]
Message-ID: <20180809114805.GM21639@ulmo> (raw)
In-Reply-To: <1533650404-18125-5-git-send-email-avienamo@nvidia.com>
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On Tue, Aug 07, 2018 at 05:00:00PM +0300, Aapo Vienamo wrote:
> Implement HS400 specific delay line calibration procedure.
>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> ---
> drivers/mmc/host/sdhci-tegra.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
Should this be before the previous patch in order to make sure the
calibration is performed as soon as the feature is available. This is
counting beans I guess, but it is technically possible for someone to
get everything up to patch 3/8 and then get the corresponding changes
in the DTS files to enable the mode and then have HS400 enabled without
this calibration.
Thierry
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index d81143b..d0b68b7 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -56,6 +56,12 @@
> #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
> #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
>
> +#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0
> +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
> +
> +#define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc
> +#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31)
> +
> #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
> #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
>
> @@ -584,6 +590,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 val)
> sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
> }
>
> +static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
> +{
> + u32 reg;
> + int err;
> +
> + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
> + reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
> + sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
Is this self-clearing? Or do we need to clear it manually in order for
a subsequent calibration procedure to succeed?
Thierry
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next prev parent reply other threads:[~2018-08-09 11:48 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-07 13:59 [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Aapo Vienamo
2018-08-07 13:59 ` [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Aapo Vienamo
2018-08-09 11:36 ` Thierry Reding
2018-08-09 11:45 ` Aapo Vienamo
2018-08-09 13:46 ` Thierry Reding
2018-08-09 14:06 ` Aapo Vienamo
2018-08-09 14:09 ` Thierry Reding
2018-08-07 13:59 ` [PATCH 2/8] mmc: tegra: Parse and program DQS trim value Aapo Vienamo
2018-08-09 11:40 ` Thierry Reding
2018-08-09 11:42 ` Thierry Reding
2018-08-07 13:59 ` [PATCH 3/8] mmc: tegra: Implement HS400 enhanced strobe Aapo Vienamo
2018-08-09 11:43 ` Thierry Reding
2018-08-09 12:22 ` Aapo Vienamo
2018-08-09 13:47 ` Thierry Reding
2018-08-07 14:00 ` [PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration Aapo Vienamo
2018-08-09 11:48 ` Thierry Reding [this message]
2018-08-09 12:29 ` Aapo Vienamo
2018-08-07 14:00 ` [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Aapo Vienamo
2018-08-09 11:49 ` Thierry Reding
2018-08-09 12:02 ` Aapo Vienamo
2018-08-09 12:23 ` Peter Geis
2018-08-09 12:37 ` Aapo Vienamo
2018-08-09 12:50 ` Peter Geis
2018-08-09 13:52 ` Thierry Reding
2018-08-07 14:00 ` [PATCH 6/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-07 14:00 ` [PATCH 7/8] arm64: dts: tegra186: Enable HS400 Aapo Vienamo
2018-08-07 14:00 ` [PATCH 8/8] arm64: dts: tegra210: " Aapo Vienamo
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