From: Thierry Reding <thierry.reding@gmail.com>
To: Aapo Vienamo <avienamo@nvidia.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value
Date: Thu, 9 Aug 2018 15:52:16 +0200 [thread overview]
Message-ID: <20180809135216.GF21639@ulmo> (raw)
In-Reply-To: <20180809150226.64657f56@dhcp-10-21-25-168>
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On Thu, Aug 09, 2018 at 03:02:26PM +0300, Aapo Vienamo wrote:
> On Thu, 9 Aug 2018 13:49:22 +0200
> Thierry Reding <thierry.reding@gmail.com> wrote:
>
> > On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote:
> > > Add the HS400 DQS trim value for Tegra186 SDMMC4.
> > >
> > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > > ---
> > > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > > index 6e9ef26..9e07bc6 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> > > @@ -313,6 +313,7 @@
> > > nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
> > > nvidia,default-tap = <0x5>;
> > > nvidia,default-trim = <0x9>;
> > > + nvidia,dqs-trim = <63>;
> > > status = "disabled";
> > > };
> > >
> >
> > Isn't this technically dependent on the board layout and as such would
> > belong in the board DTS file? Or does this value work on all existing
> > Tegra186 platforms?
>
> This value is specified as part of the controller initialization
> sequence in the TRM. I've understood that this (and other tap and trim)
> value(s) are used for compensating the propagation delay differences
> that are caused by the internal SoC layout.
Hmm... it would seem to me like the routing on a board would have a more
significant impact than the SoC internal routing. But perhaps the board-
specific routing is actually what the automatic calibration is used for?
Anyway, if it ever turns out that we need slightly different values on a
given board, we can always override the value in the board DTS file.
Thierry
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next prev parent reply other threads:[~2018-08-09 13:52 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-07 13:59 [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Aapo Vienamo
2018-08-07 13:59 ` [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Aapo Vienamo
2018-08-09 11:36 ` Thierry Reding
2018-08-09 11:45 ` Aapo Vienamo
2018-08-09 13:46 ` Thierry Reding
2018-08-09 14:06 ` Aapo Vienamo
2018-08-09 14:09 ` Thierry Reding
2018-08-07 13:59 ` [PATCH 2/8] mmc: tegra: Parse and program DQS trim value Aapo Vienamo
2018-08-09 11:40 ` Thierry Reding
2018-08-09 11:42 ` Thierry Reding
2018-08-07 13:59 ` [PATCH 3/8] mmc: tegra: Implement HS400 enhanced strobe Aapo Vienamo
2018-08-09 11:43 ` Thierry Reding
2018-08-09 12:22 ` Aapo Vienamo
2018-08-09 13:47 ` Thierry Reding
2018-08-07 14:00 ` [PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration Aapo Vienamo
2018-08-09 11:48 ` Thierry Reding
2018-08-09 12:29 ` Aapo Vienamo
2018-08-07 14:00 ` [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Aapo Vienamo
2018-08-09 11:49 ` Thierry Reding
2018-08-09 12:02 ` Aapo Vienamo
2018-08-09 12:23 ` Peter Geis
2018-08-09 12:37 ` Aapo Vienamo
2018-08-09 12:50 ` Peter Geis
2018-08-09 13:52 ` Thierry Reding [this message]
2018-08-07 14:00 ` [PATCH 6/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-07 14:00 ` [PATCH 7/8] arm64: dts: tegra186: Enable HS400 Aapo Vienamo
2018-08-07 14:00 ` [PATCH 8/8] arm64: dts: tegra210: " Aapo Vienamo
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