* [PATCH] Documentation/arm64/sve: Couple of improvements and typoes
@ 2018-08-14 10:33 Julien Grall
2018-08-31 11:03 ` Dave Martin
0 siblings, 1 reply; 2+ messages in thread
From: Julien Grall @ 2018-08-14 10:33 UTC (permalink / raw)
To: linux-doc
Cc: linux-arm-kernel, linux-kernel, catalin.marinas, will.deacon,
corbet, Dave.Martin, Julien Grall
- Fix mismatch between SVE registers (Z) and FPSIMD register (V)
- Don't prefix the path for [3] with Linux to stay consistent with
[1] and [2].
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
Documentation/arm64/sve.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt
index f128f736b4a5..7169a0ec41d8 100644
--- a/Documentation/arm64/sve.txt
+++ b/Documentation/arm64/sve.txt
@@ -200,7 +200,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg)
thread.
* Changing the vector length causes all of P0..P15, FFR and all bits of
- Z0..V31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
+ Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current
vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
flag, does not constitute a change to the vector length for this purpose.
@@ -500,7 +500,7 @@ References
[2] arch/arm64/include/uapi/asm/ptrace.h
AArch64 Linux ptrace ABI definitions
-[3] linux/Documentation/arm64/cpu-feature-registers.txt
+[3] Documentation/arm64/cpu-feature-registers.txt
[4] ARM IHI0055C
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
--
2.11.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] Documentation/arm64/sve: Couple of improvements and typoes
2018-08-14 10:33 [PATCH] Documentation/arm64/sve: Couple of improvements and typoes Julien Grall
@ 2018-08-31 11:03 ` Dave Martin
0 siblings, 0 replies; 2+ messages in thread
From: Dave Martin @ 2018-08-31 11:03 UTC (permalink / raw)
To: Julien Grall
Cc: linux-doc, corbet, catalin.marinas, will.deacon, linux-kernel,
linux-arm-kernel
On Tue, Aug 14, 2018 at 11:33:32AM +0100, Julien Grall wrote:
> - Fix mismatch between SVE registers (Z) and FPSIMD register (V)
> - Don't prefix the path for [3] with Linux to stay consistent with
> [1] and [2].
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Dave Martin <Dave.Martin@arm.com>
(in case nobody picked this up yet).
Cheers
---Dave
> ---
> Documentation/arm64/sve.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt
> index f128f736b4a5..7169a0ec41d8 100644
> --- a/Documentation/arm64/sve.txt
> +++ b/Documentation/arm64/sve.txt
> @@ -200,7 +200,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg)
> thread.
>
> * Changing the vector length causes all of P0..P15, FFR and all bits of
> - Z0..V31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
> + Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
> unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current
> vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
> flag, does not constitute a change to the vector length for this purpose.
> @@ -500,7 +500,7 @@ References
> [2] arch/arm64/include/uapi/asm/ptrace.h
> AArch64 Linux ptrace ABI definitions
>
> -[3] linux/Documentation/arm64/cpu-feature-registers.txt
> +[3] Documentation/arm64/cpu-feature-registers.txt
>
> [4] ARM IHI0055C
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
> --
> 2.11.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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2018-08-31 11:03 ` Dave Martin
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