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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	<Gustavo.Pimentel@synopsys.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Santosh Shilimkar <ssantosh@kernel.org>,
	Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [RFC PATCH 33/40] dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC
Date: Fri, 21 Sep 2018 15:51:48 +0530	[thread overview]
Message-ID: <20180921102155.22839-34-kishon@ti.com> (raw)
In-Reply-To: <20180921102155.22839-1-kishon@ti.com>

AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.

See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.

Add dt-binding documentation in order to represent all these different
configurations in device tree.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../devicetree/bindings/phy/ti-phy.txt        | 77 +++++++++++++++++++
 include/dt-bindings/phy/phy-am654-serdes.h    | 13 ++++
 2 files changed, 90 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 57dfda8a7a1d..fc2fff6b2c37 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -132,3 +132,80 @@ sata_phy: phy@4a096000 {
 	syscon-pllreset = <&scm_conf 0x3fc>;
 	#phy-cells = <0>;
 };
+
+
+TI AM654 SERDES
+
+Required properties:
+ - compatible: Should be "ti,phy-am654-serdes"
+ - reg : Address and length of the register set for the device.
+ - reg-names: Should be "serdes" which corresponds to the register space
+	populated in "reg".
+ - #phy-cells: determine the number of cells that should be given in the
+	phandle while referencing this phy. Should be "2". The 1st cell
+	corresponds to the phy type (should be one of the types specified in
+	include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
+	lane function.
+	If SERDES0 is referenced 2nd cell should be:
+		0 - USB3
+		1 - PCIe0 Lane0
+		2 - ICSS2 SGMII Lane0
+	If SERDES1 is referenced 2nd cell should be:
+		0 - PCIe1 Lane0
+		1 - PCIe0 Lane1
+		2 - ICSS2 SGMII Lane1
+ - clocks: List of clock-specifiers representing the input to the SERDES.
+	Should have 3 items representing the left input clock, external
+	reference clock and right input clock in that order.
+ - clock-output-names: List of clock names for each of the clock outputs of
+	SERDES. Should have 3 items for CMU reference clock,
+	left output clock and right output clock in that order.
+ - assigned-clocks: As defined in
+	Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - assigned-clock-parents: As defined in
+	Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - #clock-cells: Should be <1> to choose between the 3 output clocks.
+	Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+   The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
+   for selecting the correct reference clock. This can be used while
+   specifying the clocks created by SERDES.
+	=> AM654_SERDES_CMU_REFCLK
+	=> AM654_SERDES_LO_REFCLK
+	=> AM654_SERDES_RO_REFCLK
+
+ - mux-controls: phandle to the multiplexer
+
+Example:
+
+Example for SERDES0 is given below. It has 3 clock inputs;
+left input reference clock as indicated by <&k3_clks 153 4>, external
+reference clock as indicated by <&k3_clks 153 1> and right input
+reference clock as indicated by <&serdes1 AM654_SERDES_LO_REFCLK>. (The
+right input of SERDES0 is connected to the left output of SERDES1).
+
+SERDES0 registers 3 clock outputs as indicated in clock-output-names. The
+first refers to the CMU reference clock, second refers to the left output
+reference clock and the third refers to the right output reference clock.
+
+The assigned-clocks and assigned-clock-parents is used here to set the
+parent of left input reference clock to MAINHSDIV_CLKOUT4 and parent of
+CMU reference clock to left input reference clock.
+
+serdes0: serdes@900000 {
+	compatible = "ti,phy-am654-serdes";
+	reg = <0x0 0x900000 0x0 0x2000>;
+	reg-names = "serdes";
+	#phy-cells = <2>;
+	power-domains = <&k3_pds 153>;
+	clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
+			<&serdes1 AM654_SERDES_LO_REFCLK>;
+	clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk",
+				"serdes0_ro_refclk";
+	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+	assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+	ti,serdes-clk = <&serdes0_clk>;
+	mux-controls = <&serdes_mux 0>;
+	#clock-cells = <1>;
+	status = "disabled";
+};
diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h
new file mode 100644
index 000000000000..e8d901729ed9
--- /dev/null
+++ b/include/dt-bindings/phy/phy-am654-serdes.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for AM654 SERDES.
+ */
+
+#ifndef _DT_BINDINGS_AM654_SERDES
+#define _DT_BINDINGS_AM654_SERDES
+
+#define AM654_SERDES_CMU_REFCLK	0
+#define AM654_SERDES_LO_REFCLK	1
+#define AM654_SERDES_RO_REFCLK	2
+
+#endif /* _DT_BINDINGS_AM654_SERDES */
-- 
2.17.1


  parent reply	other threads:[~2018-09-21 10:25 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21 10:21 [RFC PATCH 00/40] Cleanup pci-keystone.c and Add AM654 PCIe Support Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 01/40] PCI: keystone: Use quirk to limit MRRS for K2G Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 02/40] PCI: keystone: Use quirk to set MRRS for PCI host bridge Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 03/40] PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 04/40] PCI: keystone: Do not initiate link training multiple times Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 05/40] PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 06/40] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 07/40] PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 08/40] PCI: keystone: Cleanup MSI/legacy interrupt configuration and handling Kishon Vijay Abraham I
2021-07-03 21:01   ` Krzysztof Wilczyński
2021-07-05  8:21     ` Kishon Vijay Abraham I
2021-07-06 20:34       ` Krzysztof Wilczyński
2018-09-21 10:21 ` [RFC PATCH 09/40] PCI: keystone: Remove redundant platform_set_drvdata Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 10/40] PCI: keystone: Use uniform function naming convention Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 11/40] dt-bindings: PCI: keystone: Add bindings to get device control module Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 12/40] PCI: keystone: Use syscon APIs to get device id from " Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 13/40] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
     [not found]   ` <5baa1b0e.1c69fb81.4f57b.32f7@mx.google.com>
2018-11-02  7:19     ` Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 14/40] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 15/40] PCI: keystone: Cleanup PHY handling Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 16/40] PCI: keystone: Invoke pm_runtime APIs to enable clock Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 17/40] PCI: keystone: Cleanup configuration space access Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 18/40] PCI: keystone: Get number of OB windows from DT and cleanup MEM space configuration Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 19/40] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 20/40] PCI: keystone: Cleanup ks_pcie_link_up() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 21/40] PCI: keystone: Add debug error message for all errors Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 22/40] PCI: keystone: Reorder header file in alphabetical order Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 23/40] PCI: keystone: Cleanup macros defined in pci-keystone.c Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 24/40] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 25/40] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 26/40] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 27/40] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 28/40] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 29/40] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 30/40] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 31/40] PCI: keystone: Add support for PCIe in AM654x Platforms Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 32/40] phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback Kishon Vijay Abraham I
2018-09-21 10:21 ` Kishon Vijay Abraham I [this message]
2018-09-21 10:21 ` [RFC PATCH 34/40] phy: ti: Add a new SERDES driver for TI's AM654x SoC Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 35/40] ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 36/40] arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its Kishon Vijay Abraham I
2018-09-21 19:42   ` Nishanth Menon
2018-09-21 10:21 ` [RFC PATCH 37/40] arm64: dts: k3-am6: Add Main System Control Module node Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 38/40] arm64: dts: k3-am6: Add mux-controller dt node required for muxing SERDES Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 39/40] arm64: dts: k3-am6: Add SERDES DT node Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 40/40] arm64: dts: k3-am6: Add Root Complex PCIe dt node Kishon Vijay Abraham I
2018-10-12 13:47 ` [RFC PATCH 00/40] Cleanup pci-keystone.c and Add AM654 PCIe Support Lorenzo Pieralisi

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