[PATCH 0/4] spi: add support for octal mode data transfer

[PATCH 0/4] spi: add support for octal mode data transfer

[Yogesh Gaur]

Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).

Patch series 
* Add support for octal mode flags and parsing of same in spi driver.
* Add octal data communication commands required for mt35xu512aba [1] flash.
* Add support for Read and Write proto for (1-1-8/1-8-8) mode.
* Add mode bit required for octal mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].

Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.

 root@lxxx:~# cat /proc/mtd
 dev:    size   erasesize  name
 mtd0: 04000000 00001000 "spi0.0"
 mtd1: 04000000 00001000 "spi0.1"
 root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
 Copied 16777216 bytes from address 0x00000000 in flash to 0read
 
 real    0m2.792s
 user    0m0.000s
 sys     0m2.790s
 root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
 Copied 16777216 bytes from address 0x00000000 in flash to 0read
 
 real    0m0.441s
 user    0m0.000s
 sys     0m0.440s
 root@ls1012ardb:~#

 Flash device MTD0 configured in 1-1-1 protocol.
 Flash device MTD1 configured in 1-1-8 protocol.

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=66317
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=66887

Yogesh Gaur (4):
  spi: add support for octal I/O data transfer
  mtd: spi-nor: add support for octal mode data transfer
  spi: nxp-fspi: add mode flag bit for octal support
  arm64: dts: lx2160a: update fspi node

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  4 ++++
 drivers/mtd/devices/m25p80.c                      |  9 ++++++++-
 drivers/mtd/spi-nor/spi-nor.c                     | 14 +++++++++++++-
 drivers/spi/spi-nxp-fspi.c                        |  4 ++--
 drivers/spi/spi.c                                 |  6 ++++++
 include/linux/mtd/spi-nor.h                       |  8 ++++++++
 include/linux/spi/spi.h                           |  2 ++
 7 files changed, 43 insertions(+), 4 deletions(-)

-- 
2.7.4

[PATCH 1/4] spi: add support for octal I/O data transfer

[Yogesh Gaur]

Add flags for Octal I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
 SPI_TX_OCTAL: transmit with 8 wires
 SPI_RX_OCTAL: receive with 8 wires

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
 drivers/spi/spi.c       | 6 ++++++
 include/linux/spi/spi.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ec395a6..80f672f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
 		case 4:
 			spi->mode |= SPI_TX_QUAD;
 			break;
+		case 8:
+			spi->mode |= SPI_TX_OCTAL;
+			break;
 		default:
 			dev_warn(&ctlr->dev,
 				"spi-tx-bus-width %d not supported\n",
@@ -1591,6 +1594,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
 		case 4:
 			spi->mode |= SPI_RX_QUAD;
 			break;
+		case 8:
+			spi->mode |= SPI_RX_OCTAL;
+			break;
 		default:
 			dev_warn(&ctlr->dev,
 				"spi-rx-bus-width %d not supported\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a64235e..2d21307 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -163,6 +163,8 @@ struct spi_device {
 #define	SPI_TX_QUAD	0x200			/* transmit with 4 wires */
 #define	SPI_RX_DUAL	0x400			/* receive with 2 wires */
 #define	SPI_RX_QUAD	0x800			/* receive with 4 wires */
+#define	SPI_TX_OCTAL	0x1000			/* transmit with 8 wires */
+#define	SPI_RX_OCTAL	0x2000			/* receive with 8 wires */
 	int			irq;
 	void			*controller_state;
 	void			*controller_data;
-- 
2.7.4

[PATCH 2/4] mtd: spi-nor: add support for octal mode data transfer

[Yogesh Gaur]

Add support for octal mode data transfer for Micron mt35xu512aba.

Unfortunately, this flash is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto detection
of Octal mode capabilities and opcodes. Therefore, this capability is
manually added using new SPI_NOR_OCTAL_READ flag.

Added support of Octal mode parsing for 'm25p80' spi-nor flash interface.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
 drivers/mtd/devices/m25p80.c  |  9 ++++++++-
 drivers/mtd/spi-nor/spi-nor.c | 14 +++++++++++++-
 include/linux/mtd/spi-nor.h   |  8 ++++++++
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index fe260cc..e22aa2b 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -182,7 +182,14 @@ static int m25p_probe(struct spi_mem *spimem)
 	spi_mem_set_drvdata(spimem, flash);
 	flash->spimem = spimem;
 
-	if (spi->mode & SPI_RX_QUAD) {
+	if (spi->mode & SPI_RX_OCTAL) {
+		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+		if (spi->mode & SPI_TX_OCTAL)
+			hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+					SNOR_HWCAPS_PP_1_1_8 |
+					SNOR_HWCAPS_PP_1_8_8);
+	} else if (spi->mode & SPI_RX_QUAD) {
 		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
 		if (spi->mode & SPI_TX_QUAD)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 6042df8..0587b9c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,7 @@ struct flash_info {
 #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
 #define USE_CLSR		BIT(14)	/* use CLSR command */
+#define SPI_NOR_OCTAL_READ	BIT(15)	/* Flash supports Octal Read */
 
 	int	(*quad_enable)(struct spi_nor *nor);
 };
@@ -208,6 +209,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
 		{ SPINOR_OP_READ_1_2_2,	SPINOR_OP_READ_1_2_2_4B },
 		{ SPINOR_OP_READ_1_1_4,	SPINOR_OP_READ_1_1_4_4B },
 		{ SPINOR_OP_READ_1_4_4,	SPINOR_OP_READ_1_4_4_4B },
+		{ SPINOR_OP_READ_1_1_8,	SPINOR_OP_READ_1_1_8_4B },
+		{ SPINOR_OP_READ_1_8_8,	SPINOR_OP_READ_1_8_8_4B },
 
 		{ SPINOR_OP_READ_1_1_1_DTR,	SPINOR_OP_READ_1_1_1_DTR_4B },
 		{ SPINOR_OP_READ_1_2_2_DTR,	SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -224,6 +227,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
 		{ SPINOR_OP_PP,		SPINOR_OP_PP_4B },
 		{ SPINOR_OP_PP_1_1_4,	SPINOR_OP_PP_1_1_4_4B },
 		{ SPINOR_OP_PP_1_4_4,	SPINOR_OP_PP_1_4_4_4B },
+		{ SPINOR_OP_PP_1_1_8,	SPINOR_OP_PP_1_1_8_4B },
+		{ SPINOR_OP_PP_1_8_8,	SPINOR_OP_PP_1_8_8_4B },
 	};
 
 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -1114,7 +1119,7 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 
 	/* Micron */
-	{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
+	{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 
 	/* PMC */
 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
@@ -2493,6 +2498,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
 					  SNOR_PROTO_1_1_4);
 	}
 
+	if (info->flags & SPI_NOR_OCTAL_READ) {
+		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
+					  0, 8, SPINOR_OP_READ_1_1_8,
+					  SNOR_PROTO_1_1_8);
+	}
+
 	/* Page Program settings. */
 	params->hwcaps.mask |= SNOR_HWCAPS_PP;
 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index f43bfc5..b23c69d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
 #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8	0x8b	/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8	0xcb	/* Read data bytes (Octal I/O SPI) */
 #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
 #define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
+#define SPINOR_OP_PP_1_1_8	0x82	/* Octal page program */
+#define SPINOR_OP_PP_1_8_8	0xc2	/* Octal page program */
 #define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
 #define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
 #define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
@@ -73,9 +77,13 @@
 #define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B	0x7c	/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B	0xcc	/* Read data bytes (Octal I/O SPI) */
 #define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
 #define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B	0x84	/* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B	0x8e	/* Octal page program */
 #define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
 #define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
 #define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
-- 
2.7.4

[PATCH 3/4] spi: nxp-fspi: add mode flag bit for octal support

[Yogesh Gaur]

Add mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports octal mode data transfer.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
 drivers/spi/spi-nxp-fspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 0967651..ebab44a 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -1065,8 +1065,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
 	if (!ctlr)
 		return -ENOMEM;
 
-	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
-			  SPI_TX_DUAL | SPI_TX_QUAD;
+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
+			  SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
 
 	f = spi_controller_get_devdata(ctlr);
 	f->dev = dev;
-- 
2.7.4

[PATCH 4/4] arm64: dts: lx2160a: update fspi node

[Yogesh Gaur]

Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 1 respectively for both flashes connected at CS0 and CS1.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 901ca346..817175a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -42,6 +42,8 @@
 		m25p,fast-read;
 		spi-max-frequency = <20000000>;
 		reg = <0>;
+		spi-rx-bus-width = <8>;
+		spi-tx-bus-width = <1>;
 	};
 
 	mt35xu512aba1: flash@1 {
@@ -51,6 +53,8 @@
 		m25p,fast-read;
 		spi-max-frequency = <20000000>;
 		reg = <1>;
+		spi-rx-bus-width = <8>;
+		spi-tx-bus-width = <1>;
 	};
 };
 
-- 
2.7.4

Re: [PATCH 1/4] spi: add support for octal I/O data transfer

[Boris Brezillon]

Hi Yogesh,

On Thu,  4 Oct 2018 14:18:37 +0530
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Add flags for Octal I/O data transfer
> Required for the SPI controller which can do the data transfer (TX/RX)
> on 8 data lines e.g. NXP FlexSPI controller.
>  SPI_TX_OCTAL: transmit with 8 wires
>  SPI_RX_OCTAL: receive with 8 wires
> 
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> ---
>  drivers/spi/spi.c       | 6 ++++++
>  include/linux/spi/spi.h | 2 ++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index ec395a6..80f672f 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>  		case 4:
>  			spi->mode |= SPI_TX_QUAD;
>  			break;
> +		case 8:
> +			spi->mode |= SPI_TX_OCTAL;
> +			break;
>  		default:
>  			dev_warn(&ctlr->dev,
>  				"spi-tx-bus-width %d not supported\n",
> @@ -1591,6 +1594,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>  		case 4:
>  			spi->mode |= SPI_RX_QUAD;
>  			break;
> +		case 8:
> +			spi->mode |= SPI_RX_OCTAL;
> +			break;
>  		default:
>  			dev_warn(&ctlr->dev,
>  				"spi-rx-bus-width %d not supported\n",
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index a64235e..2d21307 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -163,6 +163,8 @@ struct spi_device {
>  #define	SPI_TX_QUAD	0x200			/* transmit with 4 wires */
>  #define	SPI_RX_DUAL	0x400			/* receive with 2 wires */
>  #define	SPI_RX_QUAD	0x800			/* receive with 4 wires */
> +#define	SPI_TX_OCTAL	0x1000			/* transmit with 8 wires */
> +#define	SPI_RX_OCTAL	0x2000			/* receive with 8 wires */
>  	int			irq;
>  	void			*controller_state;
>  	void			*controller_data;

You're still not updating spi-mem.c to check those flags and
SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8 instead
of 4).

Regards,

Boris

RE: [PATCH 1/4] spi: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, October 4, 2018 2:35 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/4] spi: add support for octal I/O data transfer
> 
> Hi Yogesh,
> 
> On Thu,  4 Oct 2018 14:18:37 +0530
> Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Add flags for Octal I/O data transfer
> > Required for the SPI controller which can do the data transfer (TX/RX)
> > on 8 data lines e.g. NXP FlexSPI controller.
> >  SPI_TX_OCTAL: transmit with 8 wires
> >  SPI_RX_OCTAL: receive with 8 wires
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > ---
> >  drivers/spi/spi.c       | 6 ++++++
> >  include/linux/spi/spi.h | 2 ++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > ec395a6..80f672f 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
> struct spi_device *spi,
> >  		case 4:
> >  			spi->mode |= SPI_TX_QUAD;
> >  			break;
> > +		case 8:
> > +			spi->mode |= SPI_TX_OCTAL;
> > +			break;
> >  		default:
> >  			dev_warn(&ctlr->dev,
> >  				"spi-tx-bus-width %d not supported\n", @@ -
> 1591,6 +1594,9 @@
> > static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> >  		case 4:
> >  			spi->mode |= SPI_RX_QUAD;
> >  			break;
> > +		case 8:
> > +			spi->mode |= SPI_RX_OCTAL;
> > +			break;
> >  		default:
> >  			dev_warn(&ctlr->dev,
> >  				"spi-rx-bus-width %d not supported\n", diff --
> git
> > a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> > a64235e..2d21307 100644
> > --- a/include/linux/spi/spi.h
> > +++ b/include/linux/spi/spi.h
> > @@ -163,6 +163,8 @@ struct spi_device {
> >  #define	SPI_TX_QUAD	0x200			/* transmit with 4
> wires */
> >  #define	SPI_RX_DUAL	0x400			/* receive with 2 wires
> */
> >  #define	SPI_RX_QUAD	0x800			/* receive with 4 wires
> */
> > +#define	SPI_TX_OCTAL	0x1000			/* transmit with 8
> wires */
> > +#define	SPI_RX_OCTAL	0x2000			/* receive with 8 wires
> */
> >  	int			irq;
> >  	void			*controller_state;
> >  	void			*controller_data;
> 
> You're still not updating spi-mem.c to check those flags and
> SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8 instead of
> 4).
> 
Yes and its strange that my octal mode communication is working fine without adding support in spi-mem.c and that's why this has been missed from me.
For this patch series, have done data read/write verification using MTD_DEBUG and JFFS2 mount utility and none of them reports data read error.
Would add octal mode related changes in this file too.

--
Regards
Yogesh Gaur.

> Regards,
> 
> Boris

Re: [PATCH 2/4] mtd: spi-nor: add support for octal mode data transfer

[Boris Brezillon]

On Thu,  4 Oct 2018 14:18:38 +0530
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Add support for octal mode data transfer for Micron mt35xu512aba.
> 
> Unfortunately, this flash is only complaint to SFDP JESD216B and does
> not seem to support newer JESD216C standard that provides auto detection
> of Octal mode capabilities and opcodes. Therefore, this capability is
> manually added using new SPI_NOR_OCTAL_READ flag.
> 
> Added support of Octal mode parsing for 'm25p80' spi-nor flash interface.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> ---
>  drivers/mtd/devices/m25p80.c  |  9 ++++++++-
>  drivers/mtd/spi-nor/spi-nor.c | 14 +++++++++++++-
>  include/linux/mtd/spi-nor.h   |  8 ++++++++

You mix a lot of changes in a single patch, please try to split it up:

1/ Add new opcodes and patch spi_nor_convert_3to4_read/program() and
   spi_nor_init_params()
2/ Modify m25p80.c to support octal mode
3/ Add a new entry for mt35xu512aba

>  3 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index fe260cc..e22aa2b 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -182,7 +182,14 @@ static int m25p_probe(struct spi_mem *spimem)
>  	spi_mem_set_drvdata(spimem, flash);
>  	flash->spimem = spimem;
>  
> -	if (spi->mode & SPI_RX_QUAD) {
> +	if (spi->mode & SPI_RX_OCTAL) {
> +		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
> +
> +		if (spi->mode & SPI_TX_OCTAL)
> +			hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
> +					SNOR_HWCAPS_PP_1_1_8 |
> +					SNOR_HWCAPS_PP_1_8_8);
> +	} else if (spi->mode & SPI_RX_QUAD) {
>  		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
>  
>  		if (spi->mode & SPI_TX_QUAD)
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 6042df8..0587b9c 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -89,6 +89,7 @@ struct flash_info {
>  #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
>  #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
>  #define USE_CLSR		BIT(14)	/* use CLSR command */
> +#define SPI_NOR_OCTAL_READ	BIT(15)	/* Flash supports Octal Read */
>  
>  	int	(*quad_enable)(struct spi_nor *nor);
>  };
> @@ -208,6 +209,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
>  		{ SPINOR_OP_READ_1_2_2,	SPINOR_OP_READ_1_2_2_4B },
>  		{ SPINOR_OP_READ_1_1_4,	SPINOR_OP_READ_1_1_4_4B },
>  		{ SPINOR_OP_READ_1_4_4,	SPINOR_OP_READ_1_4_4_4B },
> +		{ SPINOR_OP_READ_1_1_8,	SPINOR_OP_READ_1_1_8_4B },
> +		{ SPINOR_OP_READ_1_8_8,	SPINOR_OP_READ_1_8_8_4B },
>  
>  		{ SPINOR_OP_READ_1_1_1_DTR,	SPINOR_OP_READ_1_1_1_DTR_4B },
>  		{ SPINOR_OP_READ_1_2_2_DTR,	SPINOR_OP_READ_1_2_2_DTR_4B },
> @@ -224,6 +227,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
>  		{ SPINOR_OP_PP,		SPINOR_OP_PP_4B },
>  		{ SPINOR_OP_PP_1_1_4,	SPINOR_OP_PP_1_1_4_4B },
>  		{ SPINOR_OP_PP_1_4_4,	SPINOR_OP_PP_1_4_4_4B },
> +		{ SPINOR_OP_PP_1_1_8,	SPINOR_OP_PP_1_1_8_4B },
> +		{ SPINOR_OP_PP_1_8_8,	SPINOR_OP_PP_1_8_8_4B },
>  	};
>  
>  	return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
> @@ -1114,7 +1119,7 @@ static const struct flash_info spi_nor_ids[] = {
>  	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>  
>  	/* Micron */
> -	{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> +	{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
>  
>  	/* PMC */
>  	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
> @@ -2493,6 +2498,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
>  					  SNOR_PROTO_1_1_4);
>  	}
>  
> +	if (info->flags & SPI_NOR_OCTAL_READ) {
> +		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
> +		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
> +					  0, 8, SPINOR_OP_READ_1_1_8,
> +					  SNOR_PROTO_1_1_8);
> +	}
> +
>  	/* Page Program settings. */
>  	params->hwcaps.mask |= SNOR_HWCAPS_PP;
>  	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index f43bfc5..b23c69d 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -50,9 +50,13 @@
>  #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
>  #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
>  #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
> +#define SPINOR_OP_READ_1_1_8	0x8b	/* Read data bytes (Octal Output SPI) */
> +#define SPINOR_OP_READ_1_8_8	0xcb	/* Read data bytes (Octal I/O SPI) */
>  #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
>  #define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
>  #define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
> +#define SPINOR_OP_PP_1_1_8	0x82	/* Octal page program */
> +#define SPINOR_OP_PP_1_8_8	0xc2	/* Octal page program */
>  #define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
>  #define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
>  #define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
> @@ -73,9 +77,13 @@
>  #define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
>  #define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
>  #define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
> +#define SPINOR_OP_READ_1_1_8_4B	0x7c	/* Read data bytes (Octal Output SPI) */
> +#define SPINOR_OP_READ_1_8_8_4B	0xcc	/* Read data bytes (Octal I/O SPI) */
>  #define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
>  #define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
>  #define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
> +#define SPINOR_OP_PP_1_1_8_4B	0x84	/* Octal page program */
> +#define SPINOR_OP_PP_1_8_8_4B	0x8e	/* Octal page program */
>  #define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
>  #define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
>  #define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */

Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node

[Boris Brezillon]

On Thu,  4 Oct 2018 14:18:40 +0530
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Flash mt35xu512aba connected to FlexSPI controller supports
> 1-1-8 protocol.
> Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> 8 and 1 respectively for both flashes connected at CS0 and CS1.
> 
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 901ca346..817175a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -42,6 +42,8 @@
>  		m25p,fast-read;
>  		spi-max-frequency = <20000000>;
>  		reg = <0>;
> +		spi-rx-bus-width = <8>;
> +		spi-tx-bus-width = <1>;

Why 1? The flash is already flagged with SPI_NOR_OCTAL_READ, which
means only the read path will use 1-1-8 mode, so you can safely set
spi-tx-bus-width here and let the framework choose the appropriate mode
based on the flash capabilities.

>  	};
>  
>  	mt35xu512aba1: flash@1 {
> @@ -51,6 +53,8 @@
>  		m25p,fast-read;
>  		spi-max-frequency = <20000000>;
>  		reg = <1>;
> +		spi-rx-bus-width = <8>;
> +		spi-tx-bus-width = <1>;
>  	};
>  };
>  

Re: [PATCH 1/4] spi: add support for octal I/O data transfer

[Boris Brezillon]

On Thu, 4 Oct 2018 09:14:36 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Hi Boris,
> 
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:35 PM
> > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] spi: add
> > support for octal I/O data transfer
> > 
> > Hi Yogesh,
> > 
> > On Thu,  4 Oct 2018 14:18:37 +0530
> > Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> >   
> > > Add flags for Octal I/O data transfer
> > > Required for the SPI controller which can do the data transfer
> > > (TX/RX) on 8 data lines e.g. NXP FlexSPI controller.
> > >  SPI_TX_OCTAL: transmit with 8 wires
> > >  SPI_RX_OCTAL: receive with 8 wires
> > >
> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > ---
> > >  drivers/spi/spi.c       | 6 ++++++
> > >  include/linux/spi/spi.h | 2 ++
> > >  2 files changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > > ec395a6..80f672f 100644
> > > --- a/drivers/spi/spi.c
> > > +++ b/drivers/spi/spi.c
> > > @@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct
> > > spi_controller *ctlr,  
> > struct spi_device *spi,  
> > >  		case 4:
> > >  			spi->mode |= SPI_TX_QUAD;
> > >  			break;
> > > +		case 8:
> > > +			spi->mode |= SPI_TX_OCTAL;
> > > +			break;
> > >  		default:
> > >  			dev_warn(&ctlr->dev,
> > >  				"spi-tx-bus-width %d not
> > > supported\n", @@ -  
> > 1591,6 +1594,9 @@  
> > > static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> > > spi_device *spi, case 4:
> > >  			spi->mode |= SPI_RX_QUAD;
> > >  			break;
> > > +		case 8:
> > > +			spi->mode |= SPI_RX_OCTAL;
> > > +			break;
> > >  		default:
> > >  			dev_warn(&ctlr->dev,
> > >  				"spi-rx-bus-width %d not
> > > supported\n", diff --  
> > git  
> > > a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> > > a64235e..2d21307 100644
> > > --- a/include/linux/spi/spi.h
> > > +++ b/include/linux/spi/spi.h
> > > @@ -163,6 +163,8 @@ struct spi_device {
> > >  #define	SPI_TX_QUAD
> > > 0x200			/* transmit with 4  
> > wires */  
> > >  #define	SPI_RX_DUAL
> > > 0x400			/* receive with 2 wires  
> > */  
> > >  #define	SPI_RX_QUAD
> > > 0x800			/* receive with 4 wires  
> > */  
> > > +#define	SPI_TX_OCTAL
> > > 0x1000			/* transmit with 8  
> > wires */  
> > > +#define	SPI_RX_OCTAL
> > > 0x2000			/* receive with 8 wires  
> > */  
> > >  	int			irq;
> > >  	void			*controller_state;
> > >  	void			*controller_data;  
> > 
> > You're still not updating spi-mem.c to check those flags and
> > SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8
> > instead of 4).
> >   
> Yes and its strange that my octal mode communication is working fine
> without adding support in spi-mem.c and that's why this has been
> missed from me.

Are you based on top of spi-next?

Re: [PATCH 0/4] spi: add support for octal mode data transfer

[Vignesh R]

Hi Yogesh,

On Thursday 04 October 2018 02:18 PM, Yogesh Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
> 
> Patch series 
> * Add support for octal mode flags and parsing of same in spi driver.
> * Add octal data communication commands required for mt35xu512aba [1] flash.
> * Add support for Read and Write proto for (1-1-8/1-8-8) mode.
> * Add mode bit required for octal mode in nxp-fspi driver [2].
> * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
> 
> Tested on LX2160ARDB target with nxp-fspi driver, below are
> Read performance number of 1-1-1 and 1-1-8 read protocol.
> 
>  root@lxxx:~# cat /proc/mtd
>  dev:    size   erasesize  name
>  mtd0: 04000000 00001000 "spi0.0"
>  mtd1: 04000000 00001000 "spi0.1"
>  root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
>  Copied 16777216 bytes from address 0x00000000 in flash to 0read
>  
>  real    0m2.792s
>  user    0m0.000s
>  sys     0m2.790s
>  root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
>  Copied 16777216 bytes from address 0x00000000 in flash to 0read
>  
>  real    0m0.441s
>  user    0m0.000s
>  sys     0m0.440s
>  root@ls1012ardb:~#
> 
>  Flash device MTD0 configured in 1-1-1 protocol.
>  Flash device MTD1 configured in 1-1-8 protocol.
> 
> [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=66317
> [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=66887
> 
> Yogesh Gaur (4):
>   spi: add support for octal I/O data transfer
>   mtd: spi-nor: add support for octal mode data transfer
>   spi: nxp-fspi: add mode flag bit for octal support
>   arm64: dts: lx2160a: update fspi node

This is a bit confusing and difficult to follow. I suggest to order
patches such that spi-nor layer changes are at the first, then m25p80
related things, followed by spi-mem (if needed spi) changes and finally
spi-mem controller driver changes.

-- 
Regards
Vignesh

RE: [PATCH 4/4] arm64: dts: lx2160a: update fspi node

[Yogesh Narayan Gaur]

Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, October 4, 2018 2:48 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node
> 
> On Thu,  4 Oct 2018 14:18:40 +0530
> Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Flash mt35xu512aba connected to FlexSPI controller supports
> > 1-1-8 protocol.
> > Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> > 8 and 1 respectively for both flashes connected at CS0 and CS1.
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > index 901ca346..817175a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -42,6 +42,8 @@
> >  		m25p,fast-read;
> >  		spi-max-frequency = <20000000>;
> >  		reg = <0>;
> > +		spi-rx-bus-width = <8>;
> > +		spi-tx-bus-width = <1>;
> 
> Why 1? The flash is already flagged with SPI_NOR_OCTAL_READ, which means
> only the read path will use 1-1-8 mode, so you can safely set spi-tx-bus-width
> here and let the framework choose the appropriate mode based on the flash
> capabilities.

Ok.

> 
> >  	};
> >
> >  	mt35xu512aba1: flash@1 {
> > @@ -51,6 +53,8 @@
> >  		m25p,fast-read;
> >  		spi-max-frequency = <20000000>;
> >  		reg = <1>;
> > +		spi-rx-bus-width = <8>;
> > +		spi-tx-bus-width = <1>;
> >  	};
> >  };
> >

RE: [PATCH 1/4] spi: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, October 4, 2018 2:50 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/4] spi: add support for octal I/O data transfer
> 
> On Thu, 4 Oct 2018 09:14:36 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Hi Boris,
> >
> > > -----Original Message-----
> > > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > > Sent: Thursday, October 4, 2018 2:35 PM
> > > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > > linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] spi: add
> > > support for octal I/O data transfer
> > >
> > > Hi Yogesh,
> > >
> > > On Thu,  4 Oct 2018 14:18:37 +0530
> > > Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> > >
> > > > Add flags for Octal I/O data transfer Required for the SPI
> > > > controller which can do the data transfer
> > > > (TX/RX) on 8 data lines e.g. NXP FlexSPI controller.
> > > >  SPI_TX_OCTAL: transmit with 8 wires
> > > >  SPI_RX_OCTAL: receive with 8 wires
> > > >
> > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > ---
> > > >  drivers/spi/spi.c       | 6 ++++++
> > > >  include/linux/spi/spi.h | 2 ++
> > > >  2 files changed, 8 insertions(+)
> > > >
> > > > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > > > ec395a6..80f672f 100644
> > > > --- a/drivers/spi/spi.c
> > > > +++ b/drivers/spi/spi.c
> > > > @@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct
> > > > spi_controller *ctlr,
> > > struct spi_device *spi,
> > > >  		case 4:
> > > >  			spi->mode |= SPI_TX_QUAD;
> > > >  			break;
> > > > +		case 8:
> > > > +			spi->mode |= SPI_TX_OCTAL;
> > > > +			break;
> > > >  		default:
> > > >  			dev_warn(&ctlr->dev,
> > > >  				"spi-tx-bus-width %d not
> > > > supported\n", @@ -
> > > 1591,6 +1594,9 @@
> > > > static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> > > > spi_device *spi, case 4:
> > > >  			spi->mode |= SPI_RX_QUAD;
> > > >  			break;
> > > > +		case 8:
> > > > +			spi->mode |= SPI_RX_OCTAL;
> > > > +			break;
> > > >  		default:
> > > >  			dev_warn(&ctlr->dev,
> > > >  				"spi-rx-bus-width %d not
> > > > supported\n", diff --
> > > git
> > > > a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> > > > a64235e..2d21307 100644
> > > > --- a/include/linux/spi/spi.h
> > > > +++ b/include/linux/spi/spi.h
> > > > @@ -163,6 +163,8 @@ struct spi_device {
> > > >  #define	SPI_TX_QUAD
> > > > 0x200			/* transmit with 4
> > > wires */
> > > >  #define	SPI_RX_DUAL
> > > > 0x400			/* receive with 2 wires
> > > */
> > > >  #define	SPI_RX_QUAD
> > > > 0x800			/* receive with 4 wires
> > > */
> > > > +#define	SPI_TX_OCTAL
> > > > 0x1000			/* transmit with 8
> > > wires */
> > > > +#define	SPI_RX_OCTAL
> > > > 0x2000			/* receive with 8 wires
> > > */
> > > >  	int			irq;
> > > >  	void			*controller_state;
> > > >  	void			*controller_data;
> > >
> > > You're still not updating spi-mem.c to check those flags and
> > > SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8
> > > instead of 4).
> > >
> > Yes and its strange that my octal mode communication is working fine
> > without adding support in spi-mem.c and that's why this has been
> > missed from me.
> 
> Are you based on top of spi-next?

Ok, that might be the reason. I have rebased few days back.
Would rebase with current tip and add support in spi-mem interface too.

Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node

[Boris Brezillon]

On Thu, 4 Oct 2018 09:24:57 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Hi Boris,
> 
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:48 PM
> > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> > linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> > mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> > kernel@lists.infradead.org; computersforpeace@gmail.com;
> > frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node
> > 
> > On Thu,  4 Oct 2018 14:18:40 +0530
> > Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> >   
> > > Flash mt35xu512aba connected to FlexSPI controller supports
> > > 1-1-8 protocol.
> > > Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> > > 8 and 1 respectively for both flashes connected at CS0 and CS1.
> > >
> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > ---
> > >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > index 901ca346..817175a 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > @@ -42,6 +42,8 @@
> > >  		m25p,fast-read;
> > >  		spi-max-frequency = <20000000>;
> > >  		reg = <0>;
> > > +		spi-rx-bus-width = <8>;
> > > +		spi-tx-bus-width = <1>;  
> > 
> > Why 1? The flash is already flagged with SPI_NOR_OCTAL_READ, which means
> > only the read path will use 1-1-8 mode, so you can safely set spi-tx-bus-width

I meant 'set spi-tx-bus-width to 8' here

> > here and let the framework choose the appropriate mode based on the flash
> > capabilities.  
> 
> Ok.
> 
> >   
> > >  	};
> > >
> > >  	mt35xu512aba1: flash@1 {
> > > @@ -51,6 +53,8 @@
> > >  		m25p,fast-read;
> > >  		spi-max-frequency = <20000000>;
> > >  		reg = <1>;
> > > +		spi-rx-bus-width = <8>;
> > > +		spi-tx-bus-width = <1>;
> > >  	};
> > >  };
> > >  
> 

RE: [PATCH 4/4] arm64: dts: lx2160a: update fspi node

[Yogesh Narayan Gaur]

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, October 4, 2018 2:56 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node
> 
> On Thu, 4 Oct 2018 09:24:57 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> 
> > Hi Boris,
> >
> > > -----Original Message-----
> > > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > > Sent: Thursday, October 4, 2018 2:48 PM
> > > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > > linux-kernel@vger.kernel.org
> > > Subject: Re: [PATCH 4/4] arm64: dts: lx2160a: update fspi node
> > >
> > > On Thu,  4 Oct 2018 14:18:40 +0530
> > > Yogesh Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> > >
> > > > Flash mt35xu512aba connected to FlexSPI controller supports
> > > > 1-1-8 protocol.
> > > > Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> > > > 8 and 1 respectively for both flashes connected at CS0 and CS1.
> > > >
> > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > ---
> > > >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > index 901ca346..817175a 100644
> > > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > > > @@ -42,6 +42,8 @@
> > > >  		m25p,fast-read;
> > > >  		spi-max-frequency = <20000000>;
> > > >  		reg = <0>;
> > > > +		spi-rx-bus-width = <8>;
> > > > +		spi-tx-bus-width = <1>;
> > >
> > > Why 1? The flash is already flagged with SPI_NOR_OCTAL_READ, which
> > > means only the read path will use 1-1-8 mode, so you can safely set
> > > spi-tx-bus-width
> 
> I meant 'set spi-tx-bus-width to 8' here

Yes.

> 
> > > here and let the framework choose the appropriate mode based on the
> > > flash capabilities.
> >
> > Ok.
> >
> > >
> > > >  	};
> > > >
> > > >  	mt35xu512aba1: flash@1 {
> > > > @@ -51,6 +53,8 @@
> > > >  		m25p,fast-read;
> > > >  		spi-max-frequency = <20000000>;
> > > >  		reg = <1>;
> > > > +		spi-rx-bus-width = <8>;
> > > > +		spi-tx-bus-width = <1>;
> > > >  	};
> > > >  };
> > > >
> >

RE: [PATCH 0/4] spi: add support for octal mode data transfer

[Yogesh Narayan Gaur]

Hi Vignesh,

> -----Original Message-----
> From: Vignesh R [mailto:vigneshr@ti.com]
> Sent: Thursday, October 4, 2018 2:52 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; linux-
> mtd@lists.infradead.org; boris.brezillon@bootlin.com; marek.vasut@gmail.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org
> Cc: robh@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; linux-
> arm-kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 0/4] spi: add support for octal mode data transfer
> 
> Hi Yogesh,
> 
> On Thursday 04 October 2018 02:18 PM, Yogesh Gaur wrote:
> > Add support for octal mode IO data transfer.
> > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP
> > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
> >
> > Patch series
> > * Add support for octal mode flags and parsing of same in spi driver.
> > * Add octal data communication commands required for mt35xu512aba [1]
> flash.
> > * Add support for Read and Write proto for (1-1-8/1-8-8) mode.
> > * Add mode bit required for octal mode in nxp-fspi driver [2].
> > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
> >
> > Tested on LX2160ARDB target with nxp-fspi driver, below are Read
> > performance number of 1-1-1 and 1-1-8 read protocol.
> >
> >  root@lxxx:~# cat /proc/mtd
> >  dev:    size   erasesize  name
> >  mtd0: 04000000 00001000 "spi0.0"
> >  mtd1: 04000000 00001000 "spi0.1"
> >  root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
> > Copied 16777216 bytes from address 0x00000000 in flash to 0read
> >
> >  real    0m2.792s
> >  user    0m0.000s
> >  sys     0m2.790s
> >  root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
> > Copied 16777216 bytes from address 0x00000000 in flash to 0read
> >
> >  real    0m0.441s
> >  user    0m0.000s
> >  sys     0m0.440s
> >  root@ls1012ardb:~#
> >
> >  Flash device MTD0 configured in 1-1-1 protocol.
> >  Flash device MTD1 configured in 1-1-8 protocol.
> >
> > [1]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D66317&amp
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C7aae8ba71d80420d4
> 49f08d
> >
> 629dad44d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636742417
> 189300
> >
> 574&amp;sdata=xsSpmoRzDKJ9Z6O56kTG5pHPojjmUfSz9rB5cWQlPEM%3D&am
> p;reser
> > ved=0 [2]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D66887&amp
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C7aae8ba71d80420d4
> 49f08d
> >
> 629dad44d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636742417
> 189300
> >
> 574&amp;sdata=oFsfTtpt0GDi3y0Fi%2B%2F9SFp8ZvbwPPe5qMNFIwVw7wE%3D
> &amp;r
> > eserved=0
> >
> > Yogesh Gaur (4):
> >   spi: add support for octal I/O data transfer
> >   mtd: spi-nor: add support for octal mode data transfer
> >   spi: nxp-fspi: add mode flag bit for octal support
> >   arm64: dts: lx2160a: update fspi node
> 
> This is a bit confusing and difficult to follow. I suggest to order patches such that
> spi-nor layer changes are at the first, then m25p80 related things, followed by
> spi-mem (if needed spi) changes and finally spi-mem controller driver changes.
> 

Thanks for the comment.
Would change the patch order as suggested and break the functionality in small patches as suggested by Boris.

--
Regards
Yogesh Gaur

> --
> Regards
> Vignesh

RE: [PATCH 1/4] spi: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Hi Boris,

> -----Original Message-----
> From: Yogesh Narayan Gaur
> Sent: Thursday, October 4, 2018 2:56 PM
> To: 'Boris Brezillon' <boris.brezillon@bootlin.com>
> Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> kernel@lists.infradead.org; computersforpeace@gmail.com;
> frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH 1/4] spi: add support for octal I/O data transfer
> 
> Hi Boris,
> 
> > -----Original Message-----
> > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:50 PM
> > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH 1/4] spi: add support for octal I/O data transfer
> >
> > On Thu, 4 Oct 2018 09:14:36 +0000
> > Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> >
> > > Hi Boris,
> > >
> > > > -----Original Message-----
> > > > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > > > Sent: Thursday, October 4, 2018 2:35 PM
> > > > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > > > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > > > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > > > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > > > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > > > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > > > linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] spi: add
> > > > support for octal I/O data transfer
> > > >
> > > > Hi Yogesh,
> > > >
[...]
> > > > > +#define	SPI_RX_OCTAL
> > > > > 0x2000			/* receive with 8 wires
> > > > */
> > > > >  	int			irq;
> > > > >  	void			*controller_state;
> > > > >  	void			*controller_data;
> > > >
> > > > You're still not updating spi-mem.c to check those flags and
> > > > SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8
> > > > instead of 4).
> > > >
> > > Yes and its strange that my octal mode communication is working fine
> > > without adding support in spi-mem.c and that's why this has been
> > > missed from me.
> >
> > Are you based on top of spi-next?
> 
> Ok, that might be the reason. I have rebased few days back.
> Would rebase with current tip and add support in spi-mem interface too.

I have rebased spi-next and currently on top but still my octal command support is working fine without any issue with current shared patch series, performed data sanity.

=>  git log  --pretty=oneline -3
	496c415717b8bb7d37181127fcfad0ba450eb10d mtd: spi-nor: fsl-quadspi: Don't let -EINVAL on the bus
	2336d3a7b125683c9e8b25d6efa6064310d19dbe mtd: devices: m25p80: Make sure WRITE_EN is issued before each write
	e55841874471282d32eec595997afce43a5f55c0 mtd: spi-nor: Support controllers with limited TX FIFO size

GIT Repo - 	git://git.infradead.org/linux-mtd.git
Branch -	remotes/origin/spi-nor/next

Also, I am not able to find string SPI_MEM_MAX_BUSWIDTH in current source code, can you share the GIT details where these changes are pushed.
--
Regards
Yogesh Gaur.

Re: [PATCH 1/4] spi: add support for octal I/O data transfer

[Boris Brezillon]

On Thu, 4 Oct 2018 12:07:17 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:

> Hi Boris,
> 
> > -----Original Message-----
> > From: Yogesh Narayan Gaur
> > Sent: Thursday, October 4, 2018 2:56 PM
> > To: 'Boris Brezillon' <boris.brezillon@bootlin.com>
> > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com; vigneshr@ti.com;
> > linux-spi@vger.kernel.org; devicetree@vger.kernel.org; robh@kernel.org;
> > mark.rutland@arm.com; shawnguo@kernel.org; linux-arm-
> > kernel@lists.infradead.org; computersforpeace@gmail.com;
> > frieder.schrempf@exceet.de; linux-kernel@vger.kernel.org
> > Subject: RE: [PATCH 1/4] spi: add support for octal I/O data transfer
> > 
> > Hi Boris,
> >   
> > > -----Original Message-----
> > > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > > Sent: Thursday, October 4, 2018 2:50 PM
> > > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > > linux-kernel@vger.kernel.org
> > > Subject: Re: [PATCH 1/4] spi: add support for octal I/O data transfer
> > >
> > > On Thu, 4 Oct 2018 09:14:36 +0000
> > > Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> > >  
> > > > Hi Boris,
> > > >  
> > > > > -----Original Message-----
> > > > > From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> > > > > Sent: Thursday, October 4, 2018 2:35 PM
> > > > > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> > > > > Cc: linux-mtd@lists.infradead.org; marek.vasut@gmail.com;
> > > > > vigneshr@ti.com; linux-spi@vger.kernel.org;
> > > > > devicetree@vger.kernel.org; robh@kernel.org; mark.rutland@arm.com;
> > > > > shawnguo@kernel.org; linux-arm- kernel@lists.infradead.org;
> > > > > computersforpeace@gmail.com; frieder.schrempf@exceet.de;
> > > > > linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] spi: add
> > > > > support for octal I/O data transfer
> > > > >
> > > > > Hi Yogesh,
> > > > >  
> [...]
> > > > > > +#define	SPI_RX_OCTAL
> > > > > > 0x2000			/* receive with 8 wires  
> > > > > */  
> > > > > >  	int			irq;
> > > > > >  	void			*controller_state;
> > > > > >  	void			*controller_data;  
> > > > >
> > > > > You're still not updating spi-mem.c to check those flags and
> > > > > SPI_MEM_MAX_BUSWIDTH is not updated to match the new limit (8
> > > > > instead of 4).
> > > > >  
> > > > Yes and its strange that my octal mode communication is working fine
> > > > without adding support in spi-mem.c and that's why this has been
> > > > missed from me.  
> > >
> > > Are you based on top of spi-next?  
> > 
> > Ok, that might be the reason. I have rebased few days back.
> > Would rebase with current tip and add support in spi-mem interface too.  
> 
> I have rebased spi-next and currently on top but still my octal command support is working fine without any issue with current shared patch series, performed data sanity.
> 
> =>  git log  --pretty=oneline -3  
> 	496c415717b8bb7d37181127fcfad0ba450eb10d mtd: spi-nor: fsl-quadspi: Don't let -EINVAL on the bus
> 	2336d3a7b125683c9e8b25d6efa6064310d19dbe mtd: devices: m25p80: Make sure WRITE_EN is issued before each write
> 	e55841874471282d32eec595997afce43a5f55c0 mtd: spi-nor: Support controllers with limited TX FIFO size
> 
> GIT Repo - 	git://git.infradead.org/linux-mtd.git
> Branch -	remotes/origin/spi-nor/next
> 
> Also, I am not able to find string SPI_MEM_MAX_BUSWIDTH in current source code, can you share the GIT details where these changes are pushed.

It's in Mark's tree [1] (spi-next != spi-nor/next).

[1]https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-next