From: Evan Green <evgreen@chromium.org>
To: Rob Herring <robh@kernel.org>, Andy Gross <andy.gross@linaro.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: Douglas Anderson <dianders@chromium.org>,
Stephen Boyd <swboyd@chromium.org>,
Evan Green <evgreen@chromium.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
David Brown <david.brown@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-soc@vger.kernel.org
Subject: [PATCH v4 3/5] arm64: dts: qcom: sdm845: add UFS controller
Date: Wed, 24 Oct 2018 10:27:33 -0700 [thread overview]
Message-ID: <20181024172735.154304-4-evgreen@chromium.org> (raw)
In-Reply-To: <20181024172735.154304-1-evgreen@chromium.org>
Add the UFS controller and PHY to SDM845.
Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
As Doug mentioned in v2, this should land after (or with) the driver fix
in this series.
Changes in v4: None
Changes in v3: None
Changes in v2:
- Renamed ufsphy to phy (Vivek)
- Removed #clock-cells (Vivek)
arch/arm64/boot/dts/qcom/sdm845.dtsi | 67 ++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b72bdb0a31a5..9c72edb678ec 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -808,6 +808,73 @@
};
};
+ ufshc1: ufshc@1d84000 {
+ compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x1d84000 0x2500>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy1_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ status = "disabled";
+ };
+
+ ufsphy1: phy@1d87000 {
+ compatible = "qcom,sdm845-qmp-ufs-phy";
+ reg = <0x1d87000 0x18c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ status = "disabled";
+
+ ufsphy1_lanes: lanes@1d87400 {
+ reg = <0x1d87400 0x108>,
+ <0x1d87600 0x1e0>,
+ <0x1d87c00 0x1dc>,
+ <0x1d87800 0x108>,
+ <0x1d87a00 0x1e0>;
+ #phy-cells = <0>;
+ };
+ };
+
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x40000>;
--
2.16.4
next prev parent reply other threads:[~2018-10-24 17:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 17:27 [PATCH v4 0/5] arm64: dts: qcom: sdm845: Add UFS DT nodes Evan Green
2018-10-24 17:27 ` [PATCH v4 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification Evan Green
2018-10-24 17:27 ` [PATCH v4 2/5] phy: qcom-qmp: Utilize fully-specified DT registers Evan Green
2018-10-24 18:29 ` Vivek Gautam
2018-10-24 20:36 ` Doug Anderson
2018-10-25 6:15 ` Vivek Gautam
2018-10-24 17:27 ` Evan Green [this message]
2018-10-24 17:27 ` [PATCH v4 4/5] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
2018-10-24 17:27 ` [PATCH v4 5/5] arm64: dts: qcom: sdm845: Add USB PHY lane two Evan Green
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