From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Mesih Kilinc <mesihkilinc@gmail.com>
Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org,
linux-sunxi@googlegroups.com, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>, Chen-Yu Tsai <wens@csie.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>
Subject: Re: [RFC PATCH 04/10] dma-engine: sun4i: Add support for Allwinner suniv F1C100s
Date: Mon, 3 Dec 2018 12:00:51 +0100 [thread overview]
Message-ID: <20181203110051.gp2ajxrmflvlyx7k@flea> (raw)
In-Reply-To: <df1e5fbb2b04b0e5d392ce988d04a39f1d8e5f8d.1543782328.git.mesihkilinc@gmail.com>
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On Mon, Dec 03, 2018 at 12:23:11AM +0300, Mesih Kilinc wrote:
> DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4
> DDMA channels and endpoints are different. Also F1C100s has reset bit
> for DMA in CCU. Add support for it.
>
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> ---
> drivers/dma/Kconfig | 4 ++--
> drivers/dma/sun4i-dma.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 62 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index de511db..f8a65d2 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -163,8 +163,8 @@ config DMA_SA11X0
>
> config DMA_SUN4I
> tristate "Allwinner A10 DMA SoCs support"
> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
> - default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV
> + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV)
> select DMA_ENGINE
> select DMA_VIRTUAL_CHANNELS
> help
> diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c
> index d267ff9..c0452c9 100644
> --- a/drivers/dma/sun4i-dma.c
> +++ b/drivers/dma/sun4i-dma.c
> @@ -36,7 +36,11 @@
> #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5)
> #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type)
>
> +#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24)
> +#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8)
> +
> #define SUN4I_MAX_BURST 8
> +#define SUNIV_MAX_BURST 4
>
> /** Normal DMA register values **/
>
> @@ -44,6 +48,9 @@
> #define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16
> #define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1)
>
> +#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11
> +#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1)
Also, you're not using that define anywhere
> +
> /** Normal DMA register layout **/
>
> /* Dedicated DMA source/destination address mode values */
> @@ -57,6 +64,9 @@
> #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15)
> #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6)
>
> +#define SUNIV_NDMA_CFG_CONT_MODE BIT(29)
> +#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26)
> +
Or those two.
> /** Dedicated DMA register values **/
>
> /* Dedicated DMA source/destination address mode values */
> @@ -69,6 +79,9 @@
> #define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1
> #define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1)
>
> +#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1
This is the same value
> +#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1)
> +
And this one isn't used
> /** Dedicated DMA register layout **/
>
> /* Dedicated DMA configuration register layout */
> @@ -122,6 +135,11 @@
> #define SUN4I_DMA_NR_MAX_VCHANS \
> (SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS)
>
> +#define SUNIV_NDMA_NR_MAX_CHANNELS 4
> +#define SUNIV_DDMA_NR_MAX_CHANNELS 4
> +#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1)
> +#define SUNIV_DDMA_NR_MAX_VCHANS 10
> +
I'm not sure we need those, you can just use the raw value in the
structure.
Also, how was the number of vchans calculated?
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2018-12-03 11:01 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-02 21:23 [RFC PATCH 00/10] Add support for DMA and audio codec of F1C100s Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 01/10] dma-engine: sun4i: Add a quirk to support different chips Mesih Kilinc
2018-12-03 10:54 ` Maxime Ripard
2019-01-04 15:38 ` Vinod Koul
2018-12-02 21:23 ` [RFC PATCH 02/10] dma-engine: sun4i: Add has_reset option to quirk Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 03/10] dt-bindings: dmaengine: Add Allwinner suniv F1C100s DMA Mesih Kilinc
2018-12-19 14:03 ` Rob Herring
2018-12-02 21:23 ` [RFC PATCH 04/10] dma-engine: sun4i: Add support for Allwinner suniv F1C100s Mesih Kilinc
2018-12-03 10:56 ` Maxime Ripard
2018-12-03 11:00 ` Maxime Ripard [this message]
2018-12-02 21:23 ` [RFC PATCH 05/10] ARM: dts: suniv: f1c100s: Add support for DMA Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 06/10] ASoC: sun4i-codec: Add DMA Max Burst field Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 07/10] dt-bindigs: sound: Add Allwinner suniv F1C100s Audio Codec Mesih Kilinc
2018-12-19 14:04 ` Rob Herring
2018-12-02 21:23 ` [RFC PATCH 08/10] ASoC: sun4i-codec: Add support for Allwinner suniv F1C100s Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 09/10] ARM: dts: suniv: f1c100s: Add support for Audio Codec Mesih Kilinc
2018-12-02 21:23 ` [RFC PATCH 10/10] ARM: dts: suniv: f1c100s: Activate Audio Codec for Lichee Pi Nano Mesih Kilinc
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