linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Bjorn Helgaas <bhelgaas@google.com>, <devicetree@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	linux-pci@vger.kernel.org, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>
Subject: Re: [PATCH v2 10/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO
Date: Mon, 17 Dec 2018 15:31:40 +0100	[thread overview]
Message-ID: <20181217153140.6d51b9f3@xps13> (raw)
In-Reply-To: <20181213153619.499aab66@windsurf>

Hi Thomas,

Thomas Petazzoni <thomas.petazzoni@bootlin.com> wrote on Thu, 13 Dec
2018 15:36:19 +0100:

> Hello,
> 
> On Thu, 13 Dec 2018 15:33:06 +0100, Miquel Raynal wrote:
> 
> > I will re-send a series without this patch. I think it does not hurt to
> > keep the previous patch adding the pinmux setting in the
> > Armada-37xx.dtsi file even without using it, so I will drop only this
> > patch.  
> 
> I tend to disagree here (but perhaps you'll have other arguments to
> convince me otherwise): the GPIO used for PCIe reset is a completely
> board-specific thing. You can chose whatever GPIO you want, and each
> board can be different. Therefore, there is no reason to have such a
> pinmux configuration at the SoC level (.dtsi), it should be within the
> particular board that uses that pinmux configuration.
> 
> This is a rule that we have applied to mvebu platforms in general, and
> which I believe is fairly common in many DTs.

Actually this is a pin that may be driven directly by the PCI IP and is
not board-specific (note that the patch is wrong as the functions
should be "pcie" instead of "gpio"). What is board specific is if this
pin is actually wired to the endpoint PCIe card or not.

Anyway, as seen by Gregory, the pinctrl driver must be fixed as when
selecting the "pcie1" group, the driver was poking another area making
the EspressoBin switch unstable. With a quick fix on my side I realized
the reset was not behaving at all as expected. As it is not actually
needed for suspend/resume operation (at least on my setup) I will drop
the 'reset pin' related patches in the next iteration of the series.


Thanks,
Miquèl

  reply	other threads:[~2018-12-17 14:31 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-12 10:21 [PATCH v2 00/12] Bring suspend to RAM support to PCIe Aardvark driver Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 01/12] PCI: aardvark: Configure more registers in the configuration helper Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 02/12] PCI: aardvark: Add reset GPIO support Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 03/12] PCI: aardvark: Add PHY support Miquel Raynal
2018-12-14  0:47   ` Marek Behun
2018-12-14  0:57     ` Marek Behun
2018-12-17 16:07       ` Miquel Raynal
2018-12-17 18:27         ` Baruch Siach
2018-12-18  8:12           ` Miquel Raynal
2018-12-17 21:34         ` Marek Behun
2018-12-18  8:18           ` Miquel Raynal
2018-12-18  8:23             ` Miquel Raynal
2018-12-18 13:09               ` Marek Behun
2018-12-18 13:41                 ` Miquel Raynal
2018-12-19 15:28                   ` Marek Behún
2018-12-19 16:48                     ` Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 04/12] PCI: aardvark: Add clock support Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 05/12] PCI: aardvark: Add suspend to RAM support Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 06/12] dt-bindings: PCI: aardvark: Describe the reset-gpios property Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 07/12] dt-bindings: PCI: aardvark: Describe the clocks property Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 08/12] dt-bindings: PCI: aardvark: Describe the PHY property Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 09/12] ARM64: dts: marvell: armada-37xx: declare PCIe reset pin Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 10/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO Miquel Raynal
2018-12-13 14:33   ` Miquel Raynal
2018-12-13 14:36     ` Thomas Petazzoni
2018-12-17 14:31       ` Miquel Raynal [this message]
2018-12-12 10:21 ` [PATCH v2 11/12] ARM64: dts: marvell: armada-37xx: declare PCIe clock Miquel Raynal
2018-12-12 10:21 ` [PATCH v2 12/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY Miquel Raynal

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181217153140.6d51b9f3@xps13 \
    --to=miquel.raynal@bootlin.com \
    --cc=andrew@lunn.ch \
    --cc=antoine.tenart@bootlin.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=gregory.clement@bootlin.com \
    --cc=jason@lakedaemon.net \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=maxime.chevallier@bootlin.com \
    --cc=nadavh@marvell.com \
    --cc=robh+dt@kernel.org \
    --cc=sebastian.hesselbarth@gmail.com \
    --cc=thomas.petazzoni@bootlin.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).