From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
Jingoo Han <jingoohan1@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Mark Rutland <mark.rutland@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Murali Karicheri <m-karicheri2@ti.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-arm-kernel@axis.com>
Subject: [PATCH 10/24] PCI: dwc: Enable iATU unroll for endpoint too
Date: Mon, 14 Jan 2019 18:54:10 +0530 [thread overview]
Message-ID: <20190114132424.6445-11-kishon@ti.com> (raw)
In-Reply-To: <20190114132424.6445-1-kishon@ti.com>
iatu_unroll_enabled flag is set only for Designware in host mode.
However iATU unroll can be applicable for endpoint mode too. Set
iatu_unroll_enabled flag in dw_pcie_setup which is common for
both host mode and endpoint mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../pci/controller/dwc/pcie-designware-ep.c | 4 ----
.../pci/controller/dwc/pcie-designware-host.c | 19 -------------------
drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++
3 files changed, 19 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7a2925a16ab8..d5144781005b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -515,10 +515,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
return -EINVAL;
}
- if (pci->iatu_unroll_enabled && !pci->atu_base) {
- dev_err(dev, "atu_base is not populated\n");
- return -EINVAL;
- }
ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
if (ret < 0) {
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d7184e1a7d92..1fb7eece78ab 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -629,17 +629,6 @@ static struct pci_ops dw_pcie_ops = {
.write = dw_pcie_wr_conf,
};
-static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
-{
- u32 val;
-
- val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
- if (val == 0xffffffff)
- return 1;
-
- return 0;
-}
-
void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val, ctrl, num_ctrls;
@@ -693,14 +682,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
* we should not program the ATU here.
*/
if (!pp->ops->rd_other_conf) {
- /* Get iATU unroll support */
- pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
- dev_dbg(pci->dev, "iATU unroll: %s\n",
- pci->iatu_unroll_enabled ? "enabled" : "disabled");
-
- if (pci->iatu_unroll_enabled && !pci->atu_base)
- pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
-
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM, pp->mem_base,
pp->mem_bus_addr, pp->mem_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 93ef8c31fb39..78539452c265 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -339,6 +339,17 @@ int dw_pcie_link_up(struct dw_pcie *pci)
(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
}
+static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
+{
+ u32 val;
+
+ val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+ if (val == 0xffffffff)
+ return 1;
+
+ return 0;
+}
+
void dw_pcie_setup(struct dw_pcie *pci)
{
int ret;
@@ -347,6 +358,14 @@ void dw_pcie_setup(struct dw_pcie *pci)
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
+ /* Get iATU unroll support */
+ pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
+ dev_dbg(pci->dev, "iATU unroll: %s\n",
+ pci->iatu_unroll_enabled ? "enabled" : "disabled");
+
+ if (pci->iatu_unroll_enabled && !pci->atu_base)
+ pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+
ret = of_property_read_u32(np, "num-lanes", &lanes);
if (ret)
lanes = 0;
--
2.17.1
next prev parent reply other threads:[~2019-01-14 13:26 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-14 13:24 [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 02/24] PCI: keystone: Cleanup error_irq configuration Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
2019-01-22 0:31 ` Rob Herring
2019-01-14 13:24 ` [PATCH 04/24] PCI: keystone: Perform host initialization in a single function Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 05/24] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 06/24] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2019-01-22 0:32 ` Rob Herring
2019-01-14 13:24 ` [PATCH 08/24] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2019-01-22 0:48 ` Rob Herring
2019-01-23 10:04 ` Kishon Vijay Abraham I
2019-01-14 13:24 ` Kishon Vijay Abraham I [this message]
2019-01-14 13:24 ` [PATCH 11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 12/24] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 13/24] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2019-01-22 0:48 ` Rob Herring
2019-01-14 13:24 ` [PATCH 14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 15/24] PCI: keystone: Invoke phy_reset API before enabling PHY Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 17/24] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Kishon Vijay Abraham I
2019-01-29 9:25 ` Gustavo Pimentel
2019-01-29 10:19 ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 19/24] PCI: dwc: Add callbacks for accessing dbi2 address space Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Kishon Vijay Abraham I
2019-02-04 16:40 ` [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Lorenzo Pieralisi
2019-02-06 12:50 ` Kishon Vijay Abraham I
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