From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de,
bp@alien8.de, mingo@redhat.com, ak@linux.intel.com,
eranian@google.com
Subject: Re: [PATCH V6 2/5] perf/x86/kvm: Avoid unnecessary work in guest filtering
Date: Mon, 4 Feb 2019 16:06:23 +0100 [thread overview]
Message-ID: <20190204150623.GF17528@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1548106951-4811-2-git-send-email-kan.liang@linux.intel.com>
On Mon, Jan 21, 2019 at 01:42:28PM -0800, kan.liang@linux.intel.com wrote:
So what's wrong with the below?
Installing a quirk for
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3781,7 +3781,7 @@ static const struct x86_cpu_desc isolati
{}
};
-static void intel_check_isolation(void)
+static void intel_check_pebs_isolation(void)
{
x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
}
@@ -3891,12 +3891,6 @@ static __init void intel_sandybridge_qui
cpus_read_unlock();
}
-static __init void intel_isolation_quirk(void)
-{
- x86_pmu.check_microcode = intel_check_isolation;
- intel_check_isolation();
-}
-
static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
{ PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
{ PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
@@ -4213,6 +4207,7 @@ __init int intel_pmu_init(void)
}
intel_ds_init();
+ intel_check_pebs_isolation();
x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
@@ -4239,7 +4234,6 @@ __init int intel_pmu_init(void)
x86_pmu.event_constraints = intel_core2_event_constraints;
x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
- x86_pmu.pebs_no_isolation = 1;
pr_cont("Core2 events, ");
name = "core2";
break;
@@ -4271,7 +4265,6 @@ __init int intel_pmu_init(void)
intel_pmu_pebs_data_source_nhm();
x86_add_quirk(intel_nehalem_quirk);
x86_pmu.pebs_no_tlb = 1;
- x86_pmu.pebs_no_isolation = 1;
extra_attr = nhm_format_attr;
pr_cont("Nehalem events, ");
@@ -4291,7 +4284,6 @@ __init int intel_pmu_init(void)
x86_pmu.event_constraints = intel_gen_event_constraints;
x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
- x86_pmu.pebs_no_isolation = 1;
pr_cont("Atom events, ");
name = "bonnell";
break;
@@ -4313,7 +4305,6 @@ __init int intel_pmu_init(void)
x86_pmu.extra_regs = intel_slm_extra_regs;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.cpu_events = slm_events_attrs;
- x86_pmu.pebs_no_isolation = 1;
extra_attr = slm_format_attr;
pr_cont("Silvermont events, ");
name = "silvermont";
@@ -4341,7 +4332,6 @@ __init int intel_pmu_init(void)
x86_pmu.lbr_pt_coexist = true;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.cpu_events = glm_events_attrs;
- x86_pmu.pebs_no_isolation = 1;
extra_attr = slm_format_attr;
pr_cont("Goldmont events, ");
name = "goldmont";
@@ -4369,7 +4359,6 @@ __init int intel_pmu_init(void)
x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.get_event_constraints = glp_get_event_constraints;
x86_pmu.cpu_events = glm_events_attrs;
- x86_pmu.pebs_no_isolation = 1;
/* Goldmont Plus has 4-wide pipeline */
event_attr_td_total_slots_scale_glm.event_str = "4";
extra_attr = slm_format_attr;
@@ -4403,7 +4392,6 @@ __init int intel_pmu_init(void)
X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
intel_pmu_pebs_data_source_nhm();
- x86_pmu.pebs_no_isolation = 1;
extra_attr = nhm_format_attr;
pr_cont("Westmere events, ");
name = "westmere";
@@ -4434,7 +4422,6 @@ __init int intel_pmu_init(void)
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
x86_pmu.cpu_events = snb_events_attrs;
- x86_pmu.pebs_no_isolation = 1;
mem_attr = snb_mem_events_attrs;
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
@@ -4474,7 +4461,6 @@ __init int intel_pmu_init(void)
/* all extra regs are per-cpu when HT is on */
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.pebs_no_isolation = 1;
x86_pmu.cpu_events = snb_events_attrs;
mem_attr = snb_mem_events_attrs;
@@ -4493,7 +4479,6 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_HASWELL_X:
case INTEL_FAM6_HASWELL_ULT:
case INTEL_FAM6_HASWELL_GT3E:
- x86_add_quirk(intel_isolation_quirk);
x86_add_quirk(intel_ht_bug);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -4526,7 +4511,6 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_BROADWELL_XEON_D:
case INTEL_FAM6_BROADWELL_GT3E:
case INTEL_FAM6_BROADWELL_X:
- x86_add_quirk(intel_isolation_quirk);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
@@ -4579,7 +4563,6 @@ __init int intel_pmu_init(void)
/* all extra regs are per-cpu when HT is on */
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.pebs_no_isolation = 1;
extra_attr = slm_format_attr;
pr_cont("Knights Landing/Mill events, ");
name = "knights-landing";
@@ -4590,7 +4573,6 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_KABYLAKE_MOBILE:
case INTEL_FAM6_KABYLAKE_DESKTOP:
- x86_add_quirk(intel_isolation_quirk);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
next prev parent reply other threads:[~2019-02-04 15:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-21 21:42 [PATCH V6 1/5] x86/cpufeature: Add facility to check for min microcode revisions kan.liang
2019-01-21 21:42 ` [PATCH V6 2/5] perf/x86/kvm: Avoid unnecessary work in guest filtering kan.liang
2019-02-04 15:06 ` Peter Zijlstra [this message]
2019-02-04 15:17 ` Peter Zijlstra
2019-02-04 15:39 ` Liang, Kan
2019-02-04 15:38 ` Peter Zijlstra
2019-02-04 15:43 ` Liang, Kan
2019-02-04 16:15 ` Peter Zijlstra
2019-02-04 16:18 ` Liang, Kan
2019-02-04 15:44 ` Peter Zijlstra
2019-02-04 15:57 ` Liang, Kan
2019-02-04 16:04 ` Borislav Petkov
2019-02-04 16:23 ` Liang, Kan
2019-02-04 16:41 ` Borislav Petkov
2019-02-04 16:13 ` Andi Kleen
2019-02-04 16:23 ` Peter Zijlstra
2019-02-04 16:55 ` Liang, Kan
2019-02-04 18:15 ` Borislav Petkov
2019-02-04 18:57 ` Liang, Kan
2019-02-04 19:43 ` Borislav Petkov
2019-02-04 20:37 ` Liang, Kan
2019-02-04 16:10 ` Peter Zijlstra
2019-02-04 16:16 ` Liang, Kan
2019-01-21 21:42 ` [PATCH V6 3/5] perf/x86/intel: Clean up SNB pebs quirk kan.liang
2019-01-21 21:42 ` [PATCH V6 4/5] perf/x86/intel: Clean up counter freezing quirk kan.liang
2019-01-21 21:42 ` [PATCH V6 5/5] perf/x86/intel: Add counter freezing quirk for Goldmont kan.liang
2019-02-04 14:27 ` [PATCH V6 1/5] x86/cpufeature: Add facility to check for min microcode revisions Liang, Kan
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