[PATCH 0/4] clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU)

[PATCH 0/4] clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU)

[Krzysztof Kozlowski]

Hi,

The DTS patch depends on bindings header with clock ID.  I will take it
through samsung-soc for consecutive release.


Best regards,
Krzysztof


Krzysztof Kozlowski (4):
  dt-bindings: clock: exynos: Put CLK_UART3 in order
  dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410
  clk: samsung: exynos5410: Add gate clock for ADC
  ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU

 arch/arm/boot/dts/exynos5410-odroidxu.dts |  5 +++++
 arch/arm/boot/dts/exynos5410.dtsi         |  6 ++++++
 arch/arm/boot/dts/exynos5420.dtsi         | 18 ++++++------------
 arch/arm/boot/dts/exynos54xx.dtsi         |  9 +++++++++
 drivers/clk/samsung/clk-exynos5410.c      |  1 +
 include/dt-bindings/clock/exynos5410.h    |  3 ++-
 6 files changed, 29 insertions(+), 13 deletions(-)

-- 
2.17.1

[PATCH 1/4] dt-bindings: clock: exynos: Put CLK_UART3 in order

[Krzysztof Kozlowski]

Order the CLK_UART3 by ID.  No change in functionality.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 include/dt-bindings/clock/exynos5410.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index f179eabbcdb7..5b911ede0534 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -36,6 +36,7 @@
 #define CLK_UART0		257
 #define CLK_UART1		258
 #define CLK_UART2		259
+#define CLK_UART3		260
 #define CLK_I2C0		261
 #define CLK_I2C1		262
 #define CLK_I2C2		263
@@ -44,7 +45,6 @@
 #define CLK_USI1		266
 #define CLK_USI2		267
 #define CLK_USI3		268
-#define CLK_UART3		260
 #define CLK_PWM			279
 #define CLK_MCT			315
 #define CLK_WDT			316
-- 
2.17.1

[PATCH 2/4] dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410

[Krzysztof Kozlowski]

Add ID for TSADC clock to Exynos5410.  Choose the same value of ID as in
Exynos5420 to make it simpler/compatible in future (although clock
driver code is not shared).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 include/dt-bindings/clock/exynos5410.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 5b911ede0534..86c2ad56c5ef 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -45,6 +45,7 @@
 #define CLK_USI1		266
 #define CLK_USI2		267
 #define CLK_USI3		268
+#define CLK_TSADC		270
 #define CLK_PWM			279
 #define CLK_MCT			315
 #define CLK_WDT			316
-- 
2.17.1

[PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC

[Krzysztof Kozlowski]

Add the gate clock for ADC block on Exynos5410.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/clk/samsung/clk-exynos5410.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 0a0b09591e6f..b2da2c8fa0c7 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
 	GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
 	GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
 	GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
+	GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
 	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
 
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
-- 
2.17.1

[PATCH 4/4] ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU

[Krzysztof Kozlowski]

Move the ADC from exynos5420.dtsi to a shared file between Exynos5410 and
Exynos542x: exynos54xx.dtsi.  Enable the ADC on Odroid XU board.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410-odroidxu.dts |  5 +++++
 arch/arm/boot/dts/exynos5410.dtsi         |  6 ++++++
 arch/arm/boot/dts/exynos5420.dtsi         | 18 ++++++------------
 arch/arm/boot/dts/exynos54xx.dtsi         |  9 +++++++++
 4 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index 434a7591ff63..282600a1e08d 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -87,6 +87,11 @@
 	};
 };
 
+&adc {
+	vdd-supply = <&ldo10_reg>;
+	status = "okay";
+};
+
 &audi2s0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 57fc9c949e54..e6f78b1cee7c 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -260,6 +260,12 @@
 	};
 };
 
+&adc {
+	clocks = <&clock CLK_TSADC>;
+	clock-names = "adc";
+	samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
 &arm_a15_pmu {
 	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff15880761..149badfca74d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -548,18 +548,6 @@
 			status = "disabled";
 		};
 
-		adc: adc@12d10000 {
-			compatible = "samsung,exynos-adc-v2";
-			reg = <0x12D10000 0x100>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clock CLK_TSADC>;
-			clock-names = "adc";
-			#io-channel-cells = <1>;
-			io-channel-ranges;
-			samsung,syscon-phandle = <&pmu_system_controller>;
-			status = "disabled";
-		};
-
 		hsi2c_8: i2c@12e00000 {
 			compatible = "samsung,exynos5250-hsi2c";
 			reg = <0x12E00000 0x1000>;
@@ -1363,6 +1351,12 @@
 	};
 };
 
+&adc {
+	clocks = <&clock CLK_TSADC>;
+	clock-names = "adc";
+	samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
 &dp {
 	clocks = <&clock CLK_DP1>;
 	clock-names = "dp";
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index de26e5ee0d2d..e21ed6eb6c4c 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -96,6 +96,15 @@
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		adc: adc@12d10000 {
+			compatible = "samsung,exynos-adc-v2";
+			reg = <0x12d10000 0x100>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
+			status = "disabled";
+		};
+
 		/* i2c_0-3 are defined in exynos5.dtsi */
 		hsi2c_4: i2c@12ca0000 {
 			compatible = "samsung,exynos5250-hsi2c";
-- 
2.17.1

Re: [PATCH 1/4] dt-bindings: clock: exynos: Put CLK_UART3 in order

[Chanwoo Choi]

Hi,

On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote:
> Order the CLK_UART3 by ID.  No change in functionality.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  include/dt-bindings/clock/exynos5410.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> index f179eabbcdb7..5b911ede0534 100644
> --- a/include/dt-bindings/clock/exynos5410.h
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -36,6 +36,7 @@
>  #define CLK_UART0		257
>  #define CLK_UART1		258
>  #define CLK_UART2		259
> +#define CLK_UART3		260
>  #define CLK_I2C0		261
>  #define CLK_I2C1		262
>  #define CLK_I2C2		263
> @@ -44,7 +45,6 @@
>  #define CLK_USI1		266
>  #define CLK_USI2		267
>  #define CLK_USI3		268
> -#define CLK_UART3		260
>  #define CLK_PWM			279
>  #define CLK_MCT			315
>  #define CLK_WDT			316
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 2/4] dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410

[Chanwoo Choi]

Hi,

On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote:
> Add ID for TSADC clock to Exynos5410.  Choose the same value of ID as in
> Exynos5420 to make it simpler/compatible in future (although clock
> driver code is not shared).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  include/dt-bindings/clock/exynos5410.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> index 5b911ede0534..86c2ad56c5ef 100644
> --- a/include/dt-bindings/clock/exynos5410.h
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -45,6 +45,7 @@
>  #define CLK_USI1		266
>  #define CLK_USI2		267
>  #define CLK_USI3		268
> +#define CLK_TSADC		270
>  #define CLK_PWM			279
>  #define CLK_MCT			315
>  #define CLK_WDT			316
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC

[Chanwoo Choi]

Hi,

On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote:
> Add the gate clock for ADC block on Exynos5410.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/clk/samsung/clk-exynos5410.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> index 0a0b09591e6f..b2da2c8fa0c7 100644
> --- a/drivers/clk/samsung/clk-exynos5410.c
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
>  	GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
>  	GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
>  	GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
> +	GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
>  	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
>  
>  	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> 

I checked it on Exynos5410 TRM. Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 1/4] dt-bindings: clock: exynos: Put CLK_UART3 in order

[Rob Herring]

On Tue, 12 Feb 2019 18:50:49 +0100, Krzysztof Kozlowski wrote:
> Order the CLK_UART3 by ID.  No change in functionality.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  include/dt-bindings/clock/exynos5410.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/4] dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410

[Rob Herring]

On Tue, 12 Feb 2019 18:50:50 +0100, Krzysztof Kozlowski wrote:
> Add ID for TSADC clock to Exynos5410.  Choose the same value of ID as in
> Exynos5420 to make it simpler/compatible in future (although clock
> driver code is not shared).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  include/dt-bindings/clock/exynos5410.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/4] clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU)

[Sylwester Nawrocki]

On 2/12/19 18:50, Krzysztof Kozlowski wrote:

> The DTS patch depends on bindings header with clock ID.  I will take it
> through samsung-soc for consecutive release.

> Krzysztof Kozlowski (4):
>   dt-bindings: clock: exynos: Put CLK_UART3 in order
>   dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410
>   clk: samsung: exynos5410: Add gate clock for ADC
>   ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU

I have applied first 3 patches to clk/samsung tree, thanks!
With prefix in summary line of the first 2 commits changed to
"clk: samsung: dt-bindings:".

-- 
Regards
Sylwester