* [PATCH v2 0/4] add support for the new SAM9X60's PWM controller @ 2019-02-19 10:08 Claudiu.Beznea 2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea ` (3 more replies) 0 siblings, 4 replies; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-19 10:08 UTC (permalink / raw) To: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches Cc: linux-arm-kernel, linux-pwm, devicetree, linux-kernel, Claudiu.Beznea From: Claudiu Beznea <claudiu.beznea@microchip.com> This series adds support for PWM controller of the new SAM9X60. The difference b/w this one and the provious AT91SAM9X5 is the counter size (32 bits compared with 16 bits on the previous version) thus, allowing to generate signals with bigger periods and duty cycles. This series, modifies the driver to take into account per IP counter size by embedding this information into driver's data. Changes in v2: - add reviewed-by tag to DT inding patch - move PWM_MAXV2_PRD from patch 2/4 in patch 3/4 - change commit description for patch 3/4 Claudiu Beznea (4): pwm: atmel: add struct atmel_pwm_data pwm: atmel: add support for controllers with 32 bit counters pwm: atmel: add support for SAM9X60's PWM controller pwm: atmel: add PWM binding for SAM9X60 .../devicetree/bindings/pwm/atmel-pwm.txt | 1 + drivers/pwm/pwm-atmel.c | 119 ++++++++++++++------- 2 files changed, 81 insertions(+), 39 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data 2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea @ 2019-02-19 10:08 ` Claudiu.Beznea 2019-02-21 20:13 ` Uwe Kleine-König 2019-02-19 10:08 ` [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters Claudiu.Beznea ` (2 subsequent siblings) 3 siblings, 1 reply; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-19 10:08 UTC (permalink / raw) To: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches Cc: linux-arm-kernel, linux-pwm, devicetree, linux-kernel, Claudiu.Beznea From: Claudiu Beznea <claudiu.beznea@microchip.com> Add struct atmel_pwm_data to embed different per controller information. At this stage, embed a member of type struct atmel_pwm_registers in it. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/pwm/pwm-atmel.c | 64 +++++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 530d7dc5f1b5..7e86a5266eb6 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -65,11 +65,15 @@ struct atmel_pwm_registers { u8 duty_upd; }; +struct atmel_pwm_data { + struct atmel_pwm_registers regs; +}; + struct atmel_pwm_chip { struct pwm_chip chip; struct clk *clk; void __iomem *base; - const struct atmel_pwm_registers *regs; + const struct atmel_pwm_data *data; unsigned int updated_pwms; /* ISR is cleared when read, ensure only one thread does that */ @@ -150,15 +154,15 @@ static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); u32 val; - if (atmel_pwm->regs->duty_upd == - atmel_pwm->regs->period_upd) { + if (atmel_pwm->data->regs.duty_upd == + atmel_pwm->data->regs.period_upd) { val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); val &= ~PWM_CMR_UPD_CDTY; atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); } atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->duty_upd, cdty); + atmel_pwm->data->regs.duty_upd, cdty); } static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, @@ -168,9 +172,9 @@ static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->duty, cdty); + atmel_pwm->data->regs.duty, cdty); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->period, cprd); + atmel_pwm->data->regs.period, cprd); } static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, @@ -225,7 +229,7 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, cstate.polarity == state->polarity && cstate.period == state->period) { cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->period); + atmel_pwm->data->regs.period); atmel_pwm_calculate_cdty(state, cprd, &cdty); atmel_pwm_update_cdty(chip, pwm, cdty); return 0; @@ -277,27 +281,31 @@ static const struct pwm_ops atmel_pwm_ops = { .owner = THIS_MODULE, }; -static const struct atmel_pwm_registers atmel_pwm_regs_v1 = { - .period = PWMV1_CPRD, - .period_upd = PWMV1_CUPD, - .duty = PWMV1_CDTY, - .duty_upd = PWMV1_CUPD, +static const struct atmel_pwm_data atmel_pwm_data_v1 = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, }; -static const struct atmel_pwm_registers atmel_pwm_regs_v2 = { - .period = PWMV2_CPRD, - .period_upd = PWMV2_CPRDUPD, - .duty = PWMV2_CDTY, - .duty_upd = PWMV2_CDTYUPD, +static const struct atmel_pwm_data atmel_pwm_data_v2 = { + .regs = { + .period = PWMV2_CPRD, + .period_upd = PWMV2_CPRDUPD, + .duty = PWMV2_CDTY, + .duty_upd = PWMV2_CDTYUPD, + }, }; static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", - .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1, + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1, }, { .name = "sama5d3-pwm", - .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2, + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2, }, { /* sentinel */ }, @@ -307,20 +315,20 @@ MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes); static const struct of_device_id atmel_pwm_dt_ids[] = { { .compatible = "atmel,at91sam9rl-pwm", - .data = &atmel_pwm_regs_v1, + .data = &atmel_pwm_data_v1, }, { .compatible = "atmel,sama5d3-pwm", - .data = &atmel_pwm_regs_v2, + .data = &atmel_pwm_data_v2, }, { .compatible = "atmel,sama5d2-pwm", - .data = &atmel_pwm_regs_v2, + .data = &atmel_pwm_data_v2, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); -static inline const struct atmel_pwm_registers * +static inline const struct atmel_pwm_data * atmel_pwm_get_driver_data(struct platform_device *pdev) { const struct platform_device_id *id; @@ -330,18 +338,18 @@ atmel_pwm_get_driver_data(struct platform_device *pdev) id = platform_get_device_id(pdev); - return (struct atmel_pwm_registers *)id->driver_data; + return (struct atmel_pwm_data *)id->driver_data; } static int atmel_pwm_probe(struct platform_device *pdev) { - const struct atmel_pwm_registers *regs; + const struct atmel_pwm_data *data; struct atmel_pwm_chip *atmel_pwm; struct resource *res; int ret; - regs = atmel_pwm_get_driver_data(pdev); - if (!regs) + data = atmel_pwm_get_driver_data(pdev); + if (!data) return -ENODEV; atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); @@ -373,7 +381,7 @@ static int atmel_pwm_probe(struct platform_device *pdev) atmel_pwm->chip.base = -1; atmel_pwm->chip.npwm = 4; - atmel_pwm->regs = regs; + atmel_pwm->data = data; atmel_pwm->updated_pwms = 0; mutex_init(&atmel_pwm->isr_lock); -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data 2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea @ 2019-02-21 20:13 ` Uwe Kleine-König 0 siblings, 0 replies; 11+ messages in thread From: Uwe Kleine-König @ 2019-02-21 20:13 UTC (permalink / raw) To: Claudiu.Beznea Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel On Tue, Feb 19, 2019 at 10:08:53AM +0000, Claudiu.Beznea@microchip.com wrote: > From: Claudiu Beznea <claudiu.beznea@microchip.com> > > Add struct atmel_pwm_data to embed different per controller information. At > this stage, embed a member of type struct atmel_pwm_registers in it. I'd write: Introduce a new structure to describe per controller information. For now it contains only a struct atmel_pwm_registers member which up to now is enough to describe the relevant differences and was used directly as driver data before. This prepares adding support for another similar controller that needs additional information. Other than that Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters 2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea 2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea @ 2019-02-19 10:08 ` Claudiu.Beznea 2019-02-21 20:42 ` Uwe Kleine-König 2019-02-19 10:09 ` [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller Claudiu.Beznea 2019-02-19 10:09 ` [PATCH v2 4/4] pwm: atmel: add PWM binding for SAM9X60 Claudiu.Beznea 3 siblings, 1 reply; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-19 10:08 UTC (permalink / raw) To: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches Cc: linux-arm-kernel, linux-pwm, devicetree, linux-kernel, Claudiu.Beznea From: Claudiu Beznea <claudiu.beznea@microchip.com> New SAM9X60's PWM controller use 32 bits counters thus it could generate signals with higher period and duty cycles than the old ones. Prepare the current driver to be able to work with old controllers (that uses 16 bits counters) and with the new SAM9X60's controller, by providing counters information based on compatible. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/pwm/pwm-atmel.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 7e86a5266eb6..647d063562db 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -48,15 +48,11 @@ #define PWMV2_CPRD 0x0C #define PWMV2_CPRDUPD 0x10 -/* - * Max value for duty and period - * - * Although the duty and period register is 32 bit, - * however only the LSB 16 bits are significant. - */ -#define PWM_MAX_DTY 0xFFFF -#define PWM_MAX_PRD 0xFFFF -#define PRD_MAX_PRES 10 +/* Max values for period and prescaler */ + +/* Only the LSB 16 bits are significant. */ +#define PWM_MAXV1_PRD 0xFFFF +#define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { u8 period; @@ -65,8 +61,14 @@ struct atmel_pwm_registers { u8 duty_upd; }; +struct atmel_pwm_config { + u32 max_period; + u32 max_pres; +}; + struct atmel_pwm_data { struct atmel_pwm_registers regs; + struct atmel_pwm_config cfg; }; struct atmel_pwm_chip { @@ -125,10 +127,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, cycles *= clk_get_rate(atmel_pwm->clk); do_div(cycles, NSEC_PER_SEC); - for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) + for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) (*pres)++; - if (*pres > PRD_MAX_PRES) { + if (*pres > atmel_pwm->data->cfg.max_pres) { dev_err(chip->dev, "pres exceeds the maximum value\n"); return -EINVAL; } @@ -288,6 +290,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v1 = { .duty = PWMV1_CDTY, .duty_upd = PWMV1_CUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; static const struct atmel_pwm_data atmel_pwm_data_v2 = { @@ -297,6 +304,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { .duty = PWMV2_CDTY, .duty_upd = PWMV2_CDTYUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; static const struct platform_device_id atmel_pwm_devtypes[] = { -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters 2019-02-19 10:08 ` [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters Claudiu.Beznea @ 2019-02-21 20:42 ` Uwe Kleine-König 2019-02-22 9:10 ` Claudiu.Beznea 0 siblings, 1 reply; 11+ messages in thread From: Uwe Kleine-König @ 2019-02-21 20:42 UTC (permalink / raw) To: Claudiu.Beznea Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel Hello, On Tue, Feb 19, 2019 at 10:08:57AM +0000, Claudiu.Beznea@microchip.com wrote: > From: Claudiu Beznea <claudiu.beznea@microchip.com> > > New SAM9X60's PWM controller use 32 bits counters thus it could generate > signals with higher period and duty cycles than the old ones. Prepare the > current driver to be able to work with old controllers (that uses 16 bits > counters) and with the new SAM9X60's controller, by providing counters > information based on compatible. I'd write: The PWM controller of the new SAM9X60 SoC uses 32 bit wide counters compared to 16 bit wide counters in the earlier chips. To support this add a new structure to the compatibles' data that describe the counter width and precision and make use of them instead of the hard coded values. Other than that the commit looks fine. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > drivers/pwm/pwm-atmel.c | 34 +++++++++++++++++++++++----------- > 1 file changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c > index 7e86a5266eb6..647d063562db 100644 > --- a/drivers/pwm/pwm-atmel.c > +++ b/drivers/pwm/pwm-atmel.c > @@ -48,15 +48,11 @@ > #define PWMV2_CPRD 0x0C > #define PWMV2_CPRDUPD 0x10 > > -/* > - * Max value for duty and period > - * > - * Although the duty and period register is 32 bit, > - * however only the LSB 16 bits are significant. > - */ > -#define PWM_MAX_DTY 0xFFFF > -#define PWM_MAX_PRD 0xFFFF > -#define PRD_MAX_PRES 10 > +/* Max values for period and prescaler */ > + > +/* Only the LSB 16 bits are significant. */ > +#define PWM_MAXV1_PRD 0xFFFF > +#define PRD_MAXV1_PRES 10 > > struct atmel_pwm_registers { > u8 period; > @@ -65,8 +61,14 @@ struct atmel_pwm_registers { > u8 duty_upd; > }; > > +struct atmel_pwm_config { > + u32 max_period; > + u32 max_pres; > +}; > + > struct atmel_pwm_data { > struct atmel_pwm_registers regs; > + struct atmel_pwm_config cfg; > }; > > struct atmel_pwm_chip { > @@ -125,10 +127,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, > cycles *= clk_get_rate(atmel_pwm->clk); > do_div(cycles, NSEC_PER_SEC); > > - for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) > + for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) > (*pres)++; Orthogonal to this patch, this could be calculated without a loop. Something like pres = roundup_pow_of_two(cycles); if (pres > bitwidth_of_counter_register) pres -= bitwidth_of_counter_register; else pres = 0 (where bitwidth_of_counter_register is 16 for the older PWMs and 32 for the new one). Maybe it would make more sense to put 16 into the structure describing the PWM then instead of 0xffff (which is easily calculated from 16)? If picking this up, you might have to pay attention to pick functions that support long long arguments. roundup_pow_of_two() doesn't as of now. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters 2019-02-21 20:42 ` Uwe Kleine-König @ 2019-02-22 9:10 ` Claudiu.Beznea 0 siblings, 0 replies; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-22 9:10 UTC (permalink / raw) To: u.kleine-koenig Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel On 21.02.2019 22:42, Uwe Kleine-König wrote: > Hello, > > On Tue, Feb 19, 2019 at 10:08:57AM +0000, Claudiu.Beznea@microchip.com wrote: >> From: Claudiu Beznea <claudiu.beznea@microchip.com> >> >> New SAM9X60's PWM controller use 32 bits counters thus it could generate >> signals with higher period and duty cycles than the old ones. Prepare the >> current driver to be able to work with old controllers (that uses 16 bits >> counters) and with the new SAM9X60's controller, by providing counters >> information based on compatible. > > I'd write: > > The PWM controller of the new SAM9X60 SoC uses 32 bit wide > counters compared to 16 bit wide counters in the earlier chips. > To support this add a new structure to the compatibles' data > that describe the counter width and precision and make use of > them instead of the hard coded values. > > Other than that the commit looks fine. > >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> drivers/pwm/pwm-atmel.c | 34 +++++++++++++++++++++++----------- >> 1 file changed, 23 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c >> index 7e86a5266eb6..647d063562db 100644 >> --- a/drivers/pwm/pwm-atmel.c >> +++ b/drivers/pwm/pwm-atmel.c >> @@ -48,15 +48,11 @@ >> #define PWMV2_CPRD 0x0C >> #define PWMV2_CPRDUPD 0x10 >> >> -/* >> - * Max value for duty and period >> - * >> - * Although the duty and period register is 32 bit, >> - * however only the LSB 16 bits are significant. >> - */ >> -#define PWM_MAX_DTY 0xFFFF >> -#define PWM_MAX_PRD 0xFFFF >> -#define PRD_MAX_PRES 10 >> +/* Max values for period and prescaler */ >> + >> +/* Only the LSB 16 bits are significant. */ >> +#define PWM_MAXV1_PRD 0xFFFF >> +#define PRD_MAXV1_PRES 10 >> >> struct atmel_pwm_registers { >> u8 period; >> @@ -65,8 +61,14 @@ struct atmel_pwm_registers { >> u8 duty_upd; >> }; >> >> +struct atmel_pwm_config { >> + u32 max_period; >> + u32 max_pres; >> +}; >> + >> struct atmel_pwm_data { >> struct atmel_pwm_registers regs; >> + struct atmel_pwm_config cfg; >> }; >> >> struct atmel_pwm_chip { >> @@ -125,10 +127,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, >> cycles *= clk_get_rate(atmel_pwm->clk); >> do_div(cycles, NSEC_PER_SEC); >> >> - for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) >> + for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) >> (*pres)++; > > Orthogonal to this patch, this could be calculated without a loop. > Something like > > pres = roundup_pow_of_two(cycles); > if (pres > bitwidth_of_counter_register) > pres -= bitwidth_of_counter_register; > else > pres = 0 > > (where bitwidth_of_counter_register is 16 for the older PWMs and 32 for > the new one). Maybe it would make more sense to put 16 into the > structure describing the PWM then instead of 0xffff (which is easily > calculated from 16)? If picking this up, you might have to pay > attention to pick functions that support long long arguments. > roundup_pow_of_two() doesn't as of now. I will take it into account for future patches. Thank you, Claudiu Beznea > > Best regards > Uwe > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller 2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea 2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea 2019-02-19 10:08 ` [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters Claudiu.Beznea @ 2019-02-19 10:09 ` Claudiu.Beznea 2019-02-21 20:45 ` Uwe Kleine-König 2019-02-19 10:09 ` [PATCH v2 4/4] pwm: atmel: add PWM binding for SAM9X60 Claudiu.Beznea 3 siblings, 1 reply; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-19 10:09 UTC (permalink / raw) To: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches Cc: linux-arm-kernel, linux-pwm, devicetree, linux-kernel, Claudiu.Beznea From: Claudiu Beznea <claudiu.beznea@microchip.com> Add support for SAM9X60's PWM controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 647d063562db..229cedb02770 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -52,6 +52,8 @@ /* Only the LSB 16 bits are significant. */ #define PWM_MAXV1_PRD 0xFFFF +/* All 32 bits are significant. */ +#define PWM_MAXV2_PRD 0xFFFFFFFF #define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { }, }; +static const struct atmel_pwm_data atmel_pwm_data_v3 = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, + .cfg = { + /* 32 bits to keep period and duty. */ + .max_period = PWM_MAXV2_PRD, + .max_pres = PRD_MAXV1_PRES, + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", @@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { .compatible = "atmel,sama5d2-pwm", .data = &atmel_pwm_data_v2, }, { + .compatible = "microchip,sam9x60-pwm", + .data = &atmel_pwm_data_v3, + }, { /* sentinel */ }, }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller 2019-02-19 10:09 ` [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller Claudiu.Beznea @ 2019-02-21 20:45 ` Uwe Kleine-König 2019-02-22 9:07 ` Claudiu.Beznea 0 siblings, 1 reply; 11+ messages in thread From: Uwe Kleine-König @ 2019-02-21 20:45 UTC (permalink / raw) To: Claudiu.Beznea Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: > From: Claudiu Beznea <claudiu.beznea@microchip.com> > > Add support for SAM9X60's PWM controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c > index 647d063562db..229cedb02770 100644 > --- a/drivers/pwm/pwm-atmel.c > +++ b/drivers/pwm/pwm-atmel.c > @@ -52,6 +52,8 @@ > > /* Only the LSB 16 bits are significant. */ > #define PWM_MAXV1_PRD 0xFFFF > +/* All 32 bits are significant. */ > +#define PWM_MAXV2_PRD 0xFFFFFFFF > #define PRD_MAXV1_PRES 10 > > struct atmel_pwm_registers { > @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { > }, > }; > > +static const struct atmel_pwm_data atmel_pwm_data_v3 = { Does it make more sense to call this ..._sam9x60 to match the compatible? (If yes, patch 1 should be changed accordingly.) I wonder how the naming of the defines is chosen given that pwm_data_v3 is the first that needs PWM_MAXV2_PRD. Looks inconsistent. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller 2019-02-21 20:45 ` Uwe Kleine-König @ 2019-02-22 9:07 ` Claudiu.Beznea 2019-02-22 9:27 ` Uwe Kleine-König 0 siblings, 1 reply; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-22 9:07 UTC (permalink / raw) To: u.kleine-koenig Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel On 21.02.2019 22:45, Uwe Kleine-König wrote: > On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: >> From: Claudiu Beznea <claudiu.beznea@microchip.com> >> >> Add support for SAM9X60's PWM controller. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c >> index 647d063562db..229cedb02770 100644 >> --- a/drivers/pwm/pwm-atmel.c >> +++ b/drivers/pwm/pwm-atmel.c >> @@ -52,6 +52,8 @@ >> >> /* Only the LSB 16 bits are significant. */ >> #define PWM_MAXV1_PRD 0xFFFF >> +/* All 32 bits are significant. */ >> +#define PWM_MAXV2_PRD 0xFFFFFFFF >> #define PRD_MAXV1_PRES 10 >> >> struct atmel_pwm_registers { >> @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { >> }, >> }; >> >> +static const struct atmel_pwm_data atmel_pwm_data_v3 = { > > Does it make more sense to call this ..._sam9x60 to match the > compatible? (If yes, patch 1 should be changed accordingly.) It could be changed, yep. > > I wonder how the naming of the defines is chosen given that pwm_data_v3 > is the first that needs PWM_MAXV2_PRD. Looks inconsistent. I know... I'm aware of that. The thing is controllers may differ with regards to in-flight duty update and now there is this new difference w/ regards to counters size. Renaming the objects of type atmel_pwm_data in something like atmel_pwm_data_<chip-name> as you suggested before would make things clear for you? Thank you, Claudiu Beznea > > Best regards > Uwe > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller 2019-02-22 9:07 ` Claudiu.Beznea @ 2019-02-22 9:27 ` Uwe Kleine-König 0 siblings, 0 replies; 11+ messages in thread From: Uwe Kleine-König @ 2019-02-22 9:27 UTC (permalink / raw) To: Claudiu.Beznea Cc: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, linux-arm-kernel, linux-pwm, devicetree, linux-kernel Hello, On Fri, Feb 22, 2019 at 09:07:57AM +0000, Claudiu.Beznea@microchip.com wrote: > On 21.02.2019 22:45, Uwe Kleine-König wrote: > > On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: > > I wonder how the naming of the defines is chosen given that pwm_data_v3 > > is the first that needs PWM_MAXV2_PRD. Looks inconsistent. > > I know... I'm aware of that. The thing is controllers may differ with > regards to in-flight duty update and now there is this new difference w/ > regards to counters size. > > Renaming the objects of type atmel_pwm_data in something like > atmel_pwm_data_<chip-name> as you suggested before would make things clear > for you? Yes. Naming stuff after the first SoC that hat the respective feature/quirk/property should be fine. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 4/4] pwm: atmel: add PWM binding for SAM9X60 2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea ` (2 preceding siblings ...) 2019-02-19 10:09 ` [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller Claudiu.Beznea @ 2019-02-19 10:09 ` Claudiu.Beznea 3 siblings, 0 replies; 11+ messages in thread From: Claudiu.Beznea @ 2019-02-19 10:09 UTC (permalink / raw) To: thierry.reding, robh+dt, mark.rutland, Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches Cc: linux-arm-kernel, linux-pwm, devicetree, linux-kernel, Claudiu.Beznea From: Claudiu Beznea <claudiu.beznea@microchip.com> Add PWM binding for SAM9X60 SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/pwm/atmel-pwm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt index c8c831d7b0d1..591ecdd39c7b 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt @@ -5,6 +5,7 @@ Required properties: - "atmel,at91sam9rl-pwm" - "atmel,sama5d3-pwm" - "atmel,sama5d2-pwm" + - "microchip,sam9x60-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-02-22 9:28 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-02-19 10:08 [PATCH v2 0/4] add support for the new SAM9X60's PWM controller Claudiu.Beznea 2019-02-19 10:08 ` [PATCH v2 1/4] pwm: atmel: add struct atmel_pwm_data Claudiu.Beznea 2019-02-21 20:13 ` Uwe Kleine-König 2019-02-19 10:08 ` [PATCH v2 2/4] pwm: atmel: add support for controllers with 32 bit counters Claudiu.Beznea 2019-02-21 20:42 ` Uwe Kleine-König 2019-02-22 9:10 ` Claudiu.Beznea 2019-02-19 10:09 ` [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller Claudiu.Beznea 2019-02-21 20:45 ` Uwe Kleine-König 2019-02-22 9:07 ` Claudiu.Beznea 2019-02-22 9:27 ` Uwe Kleine-König 2019-02-19 10:09 ` [PATCH v2 4/4] pwm: atmel: add PWM binding for SAM9X60 Claudiu.Beznea
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).