* [PATCH 1/4] MIPS: Loongson32: Remove ehci platform device
2019-03-12 9:15 [PATCH 0/4] Loongson-32 initial DeviceTree support Jiaxun Yang
@ 2019-03-12 9:15 ` Jiaxun Yang
2019-03-12 9:15 ` [PATCH 2/4] MIPS: Loongson32: Add DeviceTree support Jiaxun Yang
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Jiaxun Yang @ 2019-03-12 9:15 UTC (permalink / raw)
To: linux-mips; +Cc: paul.burton, keguang.zhang, linux-kernel, Jiaxun Yang
It's going to be enabled by DeviceTree
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../include/asm/mach-loongson32/platform.h | 1 -
arch/mips/loongson32/common/platform.c | 30 -------------------
arch/mips/loongson32/ls1b/board.c | 1 -
3 files changed, 32 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index 15d1de2300fe..f36c8d287b59 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -19,7 +19,6 @@ extern struct platform_device ls1x_uart_pdev;
extern struct platform_device ls1x_cpufreq_pdev;
extern struct platform_device ls1x_eth0_pdev;
extern struct platform_device ls1x_eth1_pdev;
-extern struct platform_device ls1x_ehci_pdev;
extern struct platform_device ls1x_gpio0_pdev;
extern struct platform_device ls1x_gpio1_pdev;
extern struct platform_device ls1x_rtc_pdev;
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index 0bf355c8bcb2..4b35f49e9fcb 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -10,12 +10,10 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
-#include <linux/mtd/partitions.h>
#include <linux/sizes.h>
#include <linux/phy.h>
#include <linux/serial_8250.h>
#include <linux/stmmac.h>
-#include <linux/usb/ehci_pdriver.h>
#include <platform.h>
#include <loongson1.h>
@@ -255,34 +253,6 @@ struct platform_device ls1x_gpio1_pdev = {
.resource = ls1x_gpio1_resources,
};
-/* USB EHCI */
-static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ls1x_ehci_resources[] = {
- [0] = {
- .start = LS1X_EHCI_BASE,
- .end = LS1X_EHCI_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = LS1X_EHCI_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct usb_ehci_pdata ls1x_ehci_pdata = {
-};
-
-struct platform_device ls1x_ehci_pdev = {
- .name = "ehci-platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(ls1x_ehci_resources),
- .resource = ls1x_ehci_resources,
- .dev = {
- .dma_mask = &ls1x_ehci_dmamask,
- .platform_data = &ls1x_ehci_pdata,
- },
-};
/* Real Time Clock */
void __init ls1x_rtc_set_extclk(struct platform_device *pdev)
diff --git a/arch/mips/loongson32/ls1b/board.c b/arch/mips/loongson32/ls1b/board.c
index 447b15fc0a2b..74f7b530d9b1 100644
--- a/arch/mips/loongson32/ls1b/board.c
+++ b/arch/mips/loongson32/ls1b/board.c
@@ -42,7 +42,6 @@ static struct platform_device *ls1b_platform_devices[] __initdata = {
&ls1x_cpufreq_pdev,
&ls1x_eth0_pdev,
&ls1x_eth1_pdev,
- &ls1x_ehci_pdev,
&ls1x_gpio0_pdev,
&ls1x_gpio1_pdev,
&ls1x_rtc_pdev,
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/4] MIPS: Loongson32: Add DeviceTree support
2019-03-12 9:15 [PATCH 0/4] Loongson-32 initial DeviceTree support Jiaxun Yang
2019-03-12 9:15 ` [PATCH 1/4] MIPS: Loongson32: Remove ehci platform device Jiaxun Yang
@ 2019-03-12 9:15 ` Jiaxun Yang
2019-03-12 9:15 ` [PATCH 3/4] MIPS: Loongson32: Kconfig merge CPU_LOONGSON1B&C Jiaxun Yang
2019-03-12 9:15 ` [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c Jiaxun Yang
3 siblings, 0 replies; 7+ messages in thread
From: Jiaxun Yang @ 2019-03-12 9:15 UTC (permalink / raw)
To: linux-mips; +Cc: paul.burton, keguang.zhang, linux-kernel, Jiaxun Yang
Initial DeviceTree support for loongson32
Also remove the old IRQ driver since it have been replaced
by generic LS1X_IRQ.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 5 +-
arch/mips/loongson32/common/Makefile | 2 +-
arch/mips/loongson32/common/irq.c | 196 ---------------------------
arch/mips/loongson32/common/setup.c | 18 +++
4 files changed, 23 insertions(+), 198 deletions(-)
delete mode 100644 arch/mips/loongson32/common/irq.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ddfb587c4744..15f8cc3c965f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -437,6 +437,9 @@ config LASAT
config MACH_LOONGSON32
bool "Loongson-1 family of machines"
+ select USE_OF
+ select BUILTIN_DTB
+ select LS1X_IRQ
select SYS_SUPPORTS_ZBOOT
help
This enables support for the Loongson-1 family of machines.
@@ -3024,7 +3027,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON32 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/loongson32/common/Makefile b/arch/mips/loongson32/common/Makefile
index 723b4ce3b8f0..5b29badb0950 100644
--- a/arch/mips/loongson32/common/Makefile
+++ b/arch/mips/loongson32/common/Makefile
@@ -2,4 +2,4 @@
# Makefile for common code of loongson1 based machines.
#
-obj-y += time.o irq.o platform.o prom.o reset.o setup.o
+obj-y += time.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c
deleted file mode 100644
index 635a4abe1f48..000000000000
--- a/arch/mips/loongson32/common/irq.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/irq_cpu.h>
-
-#include <loongson1.h>
-#include <irq.h>
-
-#define LS1X_INTC_REG(n, x) \
- ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
-
-#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
-#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
-#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
-#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
-#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
-#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
-
-static void ls1x_irq_ack(struct irq_data *d)
-{
- unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
- unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
-
- __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
- | (1 << bit), LS1X_INTC_INTCLR(n));
-}
-
-static void ls1x_irq_mask(struct irq_data *d)
-{
- unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
- unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
-
- __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
- & ~(1 << bit), LS1X_INTC_INTIEN(n));
-}
-
-static void ls1x_irq_mask_ack(struct irq_data *d)
-{
- unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
- unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
-
- __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
- & ~(1 << bit), LS1X_INTC_INTIEN(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
- | (1 << bit), LS1X_INTC_INTCLR(n));
-}
-
-static void ls1x_irq_unmask(struct irq_data *d)
-{
- unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
- unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
-
- __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
- | (1 << bit), LS1X_INTC_INTIEN(n));
-}
-
-static int ls1x_irq_settype(struct irq_data *d, unsigned int type)
-{
- unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
- unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
-
- switch (type) {
- case IRQ_TYPE_LEVEL_HIGH:
- __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
- | (1 << bit), LS1X_INTC_INTPOL(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
- & ~(1 << bit), LS1X_INTC_INTEDGE(n));
- break;
- case IRQ_TYPE_LEVEL_LOW:
- __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
- & ~(1 << bit), LS1X_INTC_INTPOL(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
- & ~(1 << bit), LS1X_INTC_INTEDGE(n));
- break;
- case IRQ_TYPE_EDGE_RISING:
- __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
- | (1 << bit), LS1X_INTC_INTPOL(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
- | (1 << bit), LS1X_INTC_INTEDGE(n));
- break;
- case IRQ_TYPE_EDGE_FALLING:
- __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
- & ~(1 << bit), LS1X_INTC_INTPOL(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
- | (1 << bit), LS1X_INTC_INTEDGE(n));
- break;
- case IRQ_TYPE_EDGE_BOTH:
- __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
- & ~(1 << bit), LS1X_INTC_INTPOL(n));
- __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
- | (1 << bit), LS1X_INTC_INTEDGE(n));
- break;
- case IRQ_TYPE_NONE:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct irq_chip ls1x_irq_chip = {
- .name = "LS1X-INTC",
- .irq_ack = ls1x_irq_ack,
- .irq_mask = ls1x_irq_mask,
- .irq_mask_ack = ls1x_irq_mask_ack,
- .irq_unmask = ls1x_irq_unmask,
- .irq_set_type = ls1x_irq_settype,
-};
-
-static void ls1x_irq_dispatch(int n)
-{
- u32 int_status, irq;
-
- /* Get pending sources, masked by current enables */
- int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
- __raw_readl(LS1X_INTC_INTIEN(n));
-
- if (int_status) {
- irq = LS1X_IRQ(n, __ffs(int_status));
- do_IRQ(irq);
- }
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(TIMER_IRQ);
- else if (pending & CAUSEF_IP2)
- ls1x_irq_dispatch(0); /* INT0 */
- else if (pending & CAUSEF_IP3)
- ls1x_irq_dispatch(1); /* INT1 */
- else if (pending & CAUSEF_IP4)
- ls1x_irq_dispatch(2); /* INT2 */
- else if (pending & CAUSEF_IP5)
- ls1x_irq_dispatch(3); /* INT3 */
- else if (pending & CAUSEF_IP6)
- ls1x_irq_dispatch(4); /* INT4 */
- else
- spurious_interrupt();
-
-}
-
-static struct irqaction cascade_irqaction = {
- .handler = no_action,
- .name = "cascade",
- .flags = IRQF_NO_THREAD,
-};
-
-static void __init ls1x_irq_init(int base)
-{
- int n;
-
- /* Disable interrupts and clear pending,
- * setup all IRQs as high level triggered
- */
- for (n = 0; n < INTN; n++) {
- __raw_writel(0x0, LS1X_INTC_INTIEN(n));
- __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
- __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
- /* set DMA0, DMA1 and DMA2 to edge trigger */
- __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
- }
-
-
- for (n = base; n < NR_IRQS; n++) {
- irq_set_chip_and_handler(n, &ls1x_irq_chip,
- handle_level_irq);
- }
-
- setup_irq(INT0_IRQ, &cascade_irqaction);
- setup_irq(INT1_IRQ, &cascade_irqaction);
- setup_irq(INT2_IRQ, &cascade_irqaction);
- setup_irq(INT3_IRQ, &cascade_irqaction);
-#if defined(CONFIG_LOONGSON1_LS1C)
- setup_irq(INT4_IRQ, &cascade_irqaction);
-#endif
-}
-
-void __init arch_init_irq(void)
-{
- mips_cpu_irq_init();
- ls1x_irq_init(LS1X_IRQ_BASE);
-}
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 1640744288ee..5ede65a79d6f 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -8,12 +8,30 @@
*/
#include <asm/bootinfo.h>
+#include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+#include <asm/prom.h>
+#include <asm/bootinfo.h>
#include <prom.h>
void __init plat_mem_setup(void)
{
add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+ __dt_setup_arch(__dtb_start);
+}
+
+void __init device_tree_init(void)
+{
+ unflatten_and_copy_device_tree();
+}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
}
const char *get_system_type(void)
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/4] MIPS: Loongson32: Kconfig merge CPU_LOONGSON1B&C
2019-03-12 9:15 [PATCH 0/4] Loongson-32 initial DeviceTree support Jiaxun Yang
2019-03-12 9:15 ` [PATCH 1/4] MIPS: Loongson32: Remove ehci platform device Jiaxun Yang
2019-03-12 9:15 ` [PATCH 2/4] MIPS: Loongson32: Add DeviceTree support Jiaxun Yang
@ 2019-03-12 9:15 ` Jiaxun Yang
2019-03-12 9:15 ` [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c Jiaxun Yang
3 siblings, 0 replies; 7+ messages in thread
From: Jiaxun Yang @ 2019-03-12 9:15 UTC (permalink / raw)
To: linux-mips; +Cc: paul.burton, keguang.zhang, linux-kernel, Jiaxun Yang
Loongson-1B&C have totally identical GS232 core, so merge
them into same CPU config.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 38 +++++++++-----------------------
arch/mips/include/asm/cpu-type.h | 3 +--
arch/mips/loongson32/Kconfig | 4 ++--
3 files changed, 14 insertions(+), 31 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 15f8cc3c965f..ac0b93e57ca3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1429,26 +1429,22 @@ config CPU_LOONGSON2F
have a similar programming interface with FPGA northbridge used in
Loongson2E.
-config CPU_LOONGSON1B
- bool "Loongson 1B"
- depends on SYS_HAS_CPU_LOONGSON1B
- select CPU_LOONGSON1
+config CPU_LOONGSON1
+ bool "Loongson 1"
+ depends on SYS_HAS_CPU_LOONGSON1
+ select CPU_MIPS32
+ select CPU_MIPSR2
+ select CPU_HAS_PREFETCH
+ select CPU_HAS_LOAD_STORE_LR
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ select CPU_SUPPORTS_CPUFREQ
select LEDS_GPIO_REGISTER
help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
-config CPU_LOONGSON1C
- bool "Loongson 1C"
- depends on SYS_HAS_CPU_LOONGSON1C
- select CPU_LOONGSON1
- select LEDS_GPIO_REGISTER
- help
- The Loongson 1C is a 32-bit SoC, which implements the MIPS32
- Release 1 instruction set and part of the MIPS32 Release 2
- instruction set.
-
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1866,15 +1862,6 @@ config CPU_LOONGSON2
select ARCH_HAS_PHYS_TO_DMA
select CPU_HAS_LOAD_STORE_LR
-config CPU_LOONGSON1
- bool
- select CPU_MIPS32
- select CPU_MIPSR2
- select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
- select CPU_SUPPORTS_32BIT_KERNEL
- select CPU_SUPPORTS_HIGHMEM
- select CPU_SUPPORTS_CPUFREQ
config CPU_BMIPS32_3300
select SMP_UP if SMP
@@ -1914,10 +1901,7 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
-config SYS_HAS_CPU_LOONGSON1B
- bool
-
-config SYS_HAS_CPU_LOONGSON1C
+config SYS_HAS_CPU_LOONGSON1
bool
config SYS_HAS_CPU_MIPS32_R1
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index a45af3de075d..ee17f02419a3 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -24,8 +24,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_LOONGSON3:
#endif
-#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
- defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1)
case CPU_LOONGSON1:
#endif
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 6dacc1438906..a0a00c3e2187 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -8,7 +8,7 @@ config LOONGSON1_LS1B
bool "Loongson LS1B board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
- select SYS_HAS_CPU_LOONGSON1B
+ select SYS_HAS_CPU_LOONGSON1
select DMA_NONCOHERENT
select BOOT_ELF32
select IRQ_MIPS_CPU
@@ -23,7 +23,7 @@ config LOONGSON1_LS1C
bool "Loongson LS1C board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
- select SYS_HAS_CPU_LOONGSON1C
+ select SYS_HAS_CPU_LOONGSON1
select DMA_NONCOHERENT
select BOOT_ELF32
select IRQ_MIPS_CPU
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c
2019-03-12 9:15 [PATCH 0/4] Loongson-32 initial DeviceTree support Jiaxun Yang
` (2 preceding siblings ...)
2019-03-12 9:15 ` [PATCH 3/4] MIPS: Loongson32: Kconfig merge CPU_LOONGSON1B&C Jiaxun Yang
@ 2019-03-12 9:15 ` Jiaxun Yang
2019-03-12 12:28 ` Rob Herring
3 siblings, 1 reply; 7+ messages in thread
From: Jiaxun Yang @ 2019-03-12 9:15 UTC (permalink / raw)
To: linux-mips; +Cc: paul.burton, keguang.zhang, linux-kernel, Jiaxun Yang
Add devicetree skeleton for ls1b and ls1c
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/boot/dts/loongson/Makefile | 6 ++
arch/mips/boot/dts/loongson/ls1b.dts | 21 +++++
arch/mips/boot/dts/loongson/ls1c.dts | 25 ++++++
arch/mips/boot/dts/loongson/ls1x.dtsi | 117 ++++++++++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/ls1b.dts
create mode 100644 arch/mips/boot/dts/loongson/ls1c.dts
create mode 100644 arch/mips/boot/dts/loongson/ls1x.dtsi
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..447801568f33
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_LOONGSON1_LS1B) += ls1b.dtb
+
+dtb-$(CONFIG_LOONGSON1_LS1B) += ls1c.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/ls1b.dts b/arch/mips/boot/dts/loongson/ls1b.dts
new file mode 100644
index 000000000000..6d40dc502acf
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls1b.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+/dts-v1/;
+#include <ls1x.dtsi>
+
+/ {
+ model = "Loongson LS1B";
+ compatible = "loongson,ls1b";
+
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/mips/boot/dts/loongson/ls1c.dts b/arch/mips/boot/dts/loongson/ls1c.dts
new file mode 100644
index 000000000000..778d205a586e
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls1c.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+/dts-v1/;
+#include <ls1x.dtsi>
+
+/ {
+ model = "Loongson LS1C300A";
+ compatible = "loongson,ls1c300a";
+
+};
+
+&platintc4 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/mips/boot/dts/loongson/ls1x.dtsi b/arch/mips/boot/dts/loongson/ls1x.dtsi
new file mode 100644
index 000000000000..f808e4328fd8
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls1x.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ cpu_intc: interrupt-controller {
+ #address-cells = <0>;
+ compatible = "mti,cpu-interrupt-controller";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "simple-bus";
+ ranges;
+
+
+ platintc0: interrupt-controller@1fd01040 {
+ compatible = "loongson,ls1x-intc";
+ reg = <0x1fd01040 0x18>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>;
+ };
+
+ platintc1: interrupt-controller@1fd01058 {
+ compatible = "loongson,ls1x-intc";
+ reg = <0x1fd01058 0x18>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <3>;
+ };
+
+ platintc2: interrupt-controller@1fd01070 {
+ compatible = "loongson,ls1x-intc";
+ reg = <0x1fd01070 0x18>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <4>;
+ };
+
+ platintc3: interrupt-controller@1fd01088 {
+ compatible = "loongson,ls1x-intc";
+ reg = <0x1fd01088 0x18>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <5>;
+ };
+
+ platintc4: interrupt-controller@1fd010a0 {
+ compatible = "loongson,ls1x-intc";
+ reg = <0x1fd010a0 0x18>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <6>;
+
+ status = "disabled";
+ };
+
+ ehci0: usb@1fe20000 {
+ compatible = "generic-ehci";
+ reg = <0x1fe20000 0x100>;
+ interrupt-parent = <&platintc1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ ohci0: usb@1fe28000 {
+ compatible = "generic-ohci";
+ reg = <0x1fe28000 0x100>;
+ interrupt-parent = <&platintc1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ };
+};
+\ 文件尾没有换行符
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c
2019-03-12 9:15 ` [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c Jiaxun Yang
@ 2019-03-12 12:28 ` Rob Herring
2019-03-13 1:08 ` Jiaxun Yang
0 siblings, 1 reply; 7+ messages in thread
From: Rob Herring @ 2019-03-12 12:28 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, paul.burton, keguang.zhang, Linux Kernel Mailing List
On Tue, Mar 12, 2019 at 4:16 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Add devicetree skeleton for ls1b and ls1c
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/mips/boot/dts/loongson/Makefile | 6 ++
> arch/mips/boot/dts/loongson/ls1b.dts | 21 +++++
> arch/mips/boot/dts/loongson/ls1c.dts | 25 ++++++
> arch/mips/boot/dts/loongson/ls1x.dtsi | 117 ++++++++++++++++++++++++++
> 4 files changed, 169 insertions(+)
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/ls1b.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls1c.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls1x.dtsi
>
> diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
> new file mode 100644
> index 000000000000..447801568f33
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_LOONGSON1_LS1B) += ls1b.dtb
> +
> +dtb-$(CONFIG_LOONGSON1_LS1B) += ls1c.dtb
> +
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/loongson/ls1b.dts b/arch/mips/boot/dts/loongson/ls1b.dts
> new file mode 100644
> index 000000000000..6d40dc502acf
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/ls1b.dts
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +/dts-v1/;
> +#include <ls1x.dtsi>
> +
> +/ {
> + model = "Loongson LS1B";
> + compatible = "loongson,ls1b";
Documented?
> +
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> \ No newline at end of file
Fix this.
> diff --git a/arch/mips/boot/dts/loongson/ls1c.dts b/arch/mips/boot/dts/loongson/ls1c.dts
> new file mode 100644
> index 000000000000..778d205a586e
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/ls1c.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +/dts-v1/;
> +#include <ls1x.dtsi>
> +
> +/ {
> + model = "Loongson LS1C300A";
> + compatible = "loongson,ls1c300a";
> +
> +};
> +
> +&platintc4 {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> \ No newline at end of file
> diff --git a/arch/mips/boot/dts/loongson/ls1x.dtsi b/arch/mips/boot/dts/loongson/ls1x.dtsi
> new file mode 100644
> index 000000000000..f808e4328fd8
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/ls1x.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + reg = <0>;
Needs a (documented) compatible string.
> + };
> + };
> +
> + cpu_intc: interrupt-controller {
> + #address-cells = <0>;
> + compatible = "mti,cpu-interrupt-controller";
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + compatible = "simple-bus";
> + ranges;
> +
> +
> + platintc0: interrupt-controller@1fd01040 {
> + compatible = "loongson,ls1x-intc";
> + reg = <0x1fd01040 0x18>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <2>;
> + };
> +
> + platintc1: interrupt-controller@1fd01058 {
> + compatible = "loongson,ls1x-intc";
> + reg = <0x1fd01058 0x18>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <3>;
> + };
> +
> + platintc2: interrupt-controller@1fd01070 {
> + compatible = "loongson,ls1x-intc";
> + reg = <0x1fd01070 0x18>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <4>;
> + };
> +
> + platintc3: interrupt-controller@1fd01088 {
> + compatible = "loongson,ls1x-intc";
> + reg = <0x1fd01088 0x18>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <5>;
> + };
> +
> + platintc4: interrupt-controller@1fd010a0 {
> + compatible = "loongson,ls1x-intc";
> + reg = <0x1fd010a0 0x18>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <6>;
> +
> + status = "disabled";
Some indentation problem.
> + };
> +
> + ehci0: usb@1fe20000 {
> + compatible = "generic-ehci";
It would be better to add a chip specific compatible here. Most all
USB controllers have some quirks.
> + reg = <0x1fe20000 0x100>;
> + interrupt-parent = <&platintc1>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + ohci0: usb@1fe28000 {
> + compatible = "generic-ohci";
> + reg = <0x1fe28000 0x100>;
> + interrupt-parent = <&platintc1>;
> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
Don't you need a serial port or something for a console?
> +
> + };
> +};
> +\ 文件尾没有换行符
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 4/4] MIPS: Loongson32: dts: add ls1b & ls1c
2019-03-12 12:28 ` Rob Herring
@ 2019-03-13 1:08 ` Jiaxun Yang
0 siblings, 0 replies; 7+ messages in thread
From: Jiaxun Yang @ 2019-03-13 1:08 UTC (permalink / raw)
To: Rob Herring
Cc: linux-mips, paul.burton, keguang.zhang, Linux Kernel Mailing List
Hi Rob,
Thanks for your reply, I have some questions on that:
在 2019/3/12 下午8:28, Rob Herring 写道:
> On Tue, Mar 12, 2019 at 4:16 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> Add devicetree skeleton for ls1b and ls1c
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>
>> +/ {
>> + model = "Loongson LS1B";
>> + compatible = "loongson,ls1b";
> Documented?
Should I document the vendor string or whole
"loongson,ls1b"?
>
>> +
>> +};
>> +
>> +&ehci0 {
>> + status = "okay";
>> +};
>> +
>> +&ohci0 {
>> + status = "okay";
>> +};
>> \ No newline at end of file
> Fix this.
>
>> diff --git a/arch/mips/boot/dts/loongson/ls1c.dts b/arch/mips/boot/dts/loongson/ls1c.dts
>> new file mode 100644
>> index 000000000000..778d205a586e
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/ls1c.dts
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include <ls1x.dtsi>
>> +
>> +/ {
>> + model = "Loongson LS1C300A";
>> + compatible = "loongson,ls1c300a";
>> +
>> +};
>> +
>> +&platintc4 {
>> + status = "okay";
>> +};
>> +
>> +&ehci0 {
>> + status = "okay";
>> +};
>> +
>> +&ohci0 {
>> + status = "okay";
>> +};
>> \ No newline at end of file
>> diff --git a/arch/mips/boot/dts/loongson/ls1x.dtsi b/arch/mips/boot/dts/loongson/ls1x.dtsi
>> new file mode 100644
>> index 000000000000..f808e4328fd8
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/ls1x.dtsi
>> @@ -0,0 +1,117 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + device_type = "cpu";
>> + reg = <0>;
> Needs a (documented) compatible string.
>
>
>
>> + };
>> +
>> + ehci0: usb@1fe20000 {
>> + compatible = "generic-ehci";
> It would be better to add a chip specific compatible here. Most all
> USB controllers have some quirks.
Should it be documented?
>
>> + reg = <0x1fe20000 0x100>;
>> + interrupt-parent = <&platintc1>;
>> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@1fe28000 {
>> + compatible = "generic-ohci";
>> + reg = <0x1fe28000 0x100>;
>> + interrupt-parent = <&platintc1>;
>> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
> Don't you need a serial port or something for a console?
serial port is currently added by legacy pdev code. I'm going to add it
to devicetree after rework on clk driver being sent out.
Thanks.
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 7+ messages in thread