From: kan.liang@linux.intel.com
To: peterz@infradead.org, acme@kernel.org, mingo@redhat.com,
linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 12/23] perf/core: Support a REMOVE transaction
Date: Thu, 21 Mar 2019 13:56:52 -0700 [thread overview]
Message-ID: <20190321205703.4256-13-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20190321205703.4256-1-kan.liang@linux.intel.com>
From: Andi Kleen <ak@linux.intel.com>
The TopDown events can be collected per thread/process on Icelake. To
use TopDown through RDPMC in applications, the metrics and slots MSR
values have to be saved/restored during context switching.
It is useful to have a remove transaction when the counter is
unscheduled, so that the values can be saved correctly.
Add a remove transaction to the perf core.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
Changes since V1:
- Add more explanation in change log
arch/x86/events/core.c | 3 +--
include/linux/perf_event.h | 1 +
kernel/events/core.c | 5 +++++
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 9378c6b2128f..9c14b4b3e457 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1912,8 +1912,7 @@ static inline void x86_pmu_read(struct perf_event *event)
* Set the flag to make pmu::enable() not perform the
* schedulability test, it will be performed at commit time
*
- * We only support PERF_PMU_TXN_ADD transactions. Save the
- * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
+ * Save the transaction flags and ignore non-PERF_PMU_TXN_ADD
* transactions.
*/
static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index e47ef764f613..fb258c171b2c 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -233,6 +233,7 @@ struct perf_event;
*/
#define PERF_PMU_TXN_ADD 0x1 /* txn to add/schedule event on PMU */
#define PERF_PMU_TXN_READ 0x2 /* txn to read event group from PMU */
+#define PERF_PMU_TXN_REMOVE 0x4 /* txn to remove event on PMU */
/**
* pmu::capabilities flags
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 1032a16bd186..dea8cfe2a891 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -2032,6 +2032,7 @@ group_sched_out(struct perf_event *group_event,
struct perf_cpu_context *cpuctx,
struct perf_event_context *ctx)
{
+ struct pmu *pmu = ctx->pmu;
struct perf_event *event;
if (group_event->state != PERF_EVENT_STATE_ACTIVE)
@@ -2039,6 +2040,8 @@ group_sched_out(struct perf_event *group_event,
perf_pmu_disable(ctx->pmu);
+ pmu->start_txn(pmu, PERF_PMU_TXN_REMOVE);
+
event_sched_out(group_event, cpuctx, ctx);
/*
@@ -2051,6 +2054,8 @@ group_sched_out(struct perf_event *group_event,
if (group_event->attr.exclusive)
cpuctx->exclusive = 0;
+
+ pmu->commit_txn(pmu);
}
#define DETACH_GROUP 0x01UL
--
2.17.1
next prev parent reply other threads:[~2019-03-21 20:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-21 20:56 [PATCH V2 00/23] perf: Add Icelake support kan.liang
2019-03-21 20:56 ` [PATCH V2 01/23] perf/x86: Support outputting XMM registers kan.liang
2019-03-21 20:56 ` [PATCH V2 02/23] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-21 20:56 ` [PATCH V2 03/23] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-03-21 20:56 ` [PATCH V2 04/23] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-21 21:13 ` Peter Zijlstra
2019-03-21 21:17 ` Peter Zijlstra
2019-03-21 21:20 ` Peter Zijlstra
2019-03-22 0:40 ` Liang, Kan
2019-03-22 12:30 ` Peter Zijlstra
2019-03-21 20:56 ` [PATCH V2 05/23] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-21 20:56 ` [PATCH V2 06/23] perf/x86: Support constraint ranges kan.liang
2019-03-21 21:09 ` Peter Zijlstra
2019-03-21 20:56 ` [PATCH V2 07/23] perf/x86/intel: Add Icelake support kan.liang
2019-03-21 20:56 ` [PATCH V2 08/23] perf/x86/intel/cstate: " kan.liang
2019-03-21 20:56 ` [PATCH V2 09/23] perf/x86/intel/rapl: " kan.liang
2019-03-21 20:56 ` [PATCH V2 10/23] perf/x86/msr: " kan.liang
2019-03-21 20:56 ` [PATCH V2 11/23] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-21 20:56 ` kan.liang [this message]
2019-03-21 20:56 ` [PATCH V2 13/23] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-21 20:56 ` [PATCH V2 14/23] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-21 20:56 ` [PATCH V2 15/23] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-21 20:56 ` [PATCH V2 16/23] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-21 20:56 ` [PATCH V2 17/23] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-21 20:56 ` [PATCH V2 18/23] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-03-21 20:56 ` [PATCH V2 19/23] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-21 20:57 ` [PATCH V2 20/23] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-21 20:57 ` [PATCH V2 21/23] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-21 20:57 ` [PATCH V2 22/23] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-21 20:57 ` [PATCH V2 23/23] perf vendor events intel: Add JSON files for Icelake kan.liang
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