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From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
	tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
	alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH V2 04/23] perf/x86/intel: Support adaptive PEBSv4
Date: Thu, 21 Mar 2019 22:17:10 +0100	[thread overview]
Message-ID: <20190321211710.GC7905@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20190321205703.4256-5-kan.liang@linux.intel.com>

On Thu, Mar 21, 2019 at 01:56:44PM -0700, kan.liang@linux.intel.com wrote:
> +static inline void *next_pebs_record(void *p)
> +{
> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +	unsigned int size;
> +
> +	if (x86_pmu.intel_cap.pebs_format < 4)
> +		size = x86_pmu.pebs_record_size;
> +	else
> +		size = cpuc->pebs_record_size;
> +	return p + size;
> +}

> @@ -1323,19 +1580,19 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
>  	if (base == NULL)
>  		return NULL;
>  
> -	for (at = base; at < top; at += x86_pmu.pebs_record_size) {
> -		struct pebs_record_nhm *p = at;
> +	for (at = base; at < top; at = next_pebs_record(at)) {
> +		unsigned long status = get_pebs_status(at);

afaict we do not mix base and adaptive records, and thus the above
really could use cpuc->pebs_record_size unconditionally, right?



  parent reply	other threads:[~2019-03-21 21:17 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-21 20:56 [PATCH V2 00/23] perf: Add Icelake support kan.liang
2019-03-21 20:56 ` [PATCH V2 01/23] perf/x86: Support outputting XMM registers kan.liang
2019-03-21 20:56 ` [PATCH V2 02/23] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-21 20:56 ` [PATCH V2 03/23] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-03-21 20:56 ` [PATCH V2 04/23] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-21 21:13   ` Peter Zijlstra
2019-03-21 21:17   ` Peter Zijlstra [this message]
2019-03-21 21:20   ` Peter Zijlstra
2019-03-22  0:40     ` Liang, Kan
2019-03-22 12:30       ` Peter Zijlstra
2019-03-21 20:56 ` [PATCH V2 05/23] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-21 20:56 ` [PATCH V2 06/23] perf/x86: Support constraint ranges kan.liang
2019-03-21 21:09   ` Peter Zijlstra
2019-03-21 20:56 ` [PATCH V2 07/23] perf/x86/intel: Add Icelake support kan.liang
2019-03-21 20:56 ` [PATCH V2 08/23] perf/x86/intel/cstate: " kan.liang
2019-03-21 20:56 ` [PATCH V2 09/23] perf/x86/intel/rapl: " kan.liang
2019-03-21 20:56 ` [PATCH V2 10/23] perf/x86/msr: " kan.liang
2019-03-21 20:56 ` [PATCH V2 11/23] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-21 20:56 ` [PATCH V2 12/23] perf/core: Support a REMOVE transaction kan.liang
2019-03-21 20:56 ` [PATCH V2 13/23] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-21 20:56 ` [PATCH V2 14/23] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-21 20:56 ` [PATCH V2 15/23] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-21 20:56 ` [PATCH V2 16/23] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-21 20:56 ` [PATCH V2 17/23] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-21 20:56 ` [PATCH V2 18/23] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-03-21 20:56 ` [PATCH V2 19/23] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-21 20:57 ` [PATCH V2 20/23] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-21 20:57 ` [PATCH V2 21/23] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-21 20:57 ` [PATCH V2 22/23] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-21 20:57 ` [PATCH V2 23/23] perf vendor events intel: Add JSON files for Icelake kan.liang

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