[PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list

[PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list

[Peng Ma]

Add ls1028a compatible to bindings documentation.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
depends on:
	- http://patchwork.ozlabs.org/patch/1045217/

 .../devicetree/bindings/ata/ahci-fsl-qoriq.txt     |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index 9ecc019..72fdeef 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,8 @@ Binding for Freescale QorIQ AHCI SATA Controller
 Required properties:
   - reg: Physical base address and size of the controller's register area.
   - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
-    chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc.
+    chip could be ls1021a, ls1028a, ls1043a, ls1046a, ls1088a, ls2080a,
+    lx2160a, etc.
   - clocks: Input clock specifier. Refer to common clock bindings.
   - interrupts: Interrupt specifier. Refer to interrupt binding.
 
-- 
1.7.1

[PATCH 2/3] arm64: dts: ls1028a: Corrected the SATA ecc address.

[Peng Ma]

Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the
address.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index a8cf92a..3fcbd0a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -277,7 +277,7 @@
 		sata: sata@3200000 {
 			compatible = "fsl,ls1028a-ahci";
 			reg = <0x0 0x3200000 0x0 0x10000>,
-				<0x0 0x20140520 0x0 0x4>;
+				<0x7 0x100520 0x0 0x4>;
 			reg-names = "ahci", "sata-ecc";
 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;
-- 
1.7.1

[PATCH 3/3] ahci: qoriq: add ls1028a platforms support

[Peng Ma]

Ls1028a is a new introduced soc which supports ATA3.0

Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
depends on:
	- http://patchwork.ozlabs.org/patch/1045218/

 drivers/ata/ahci_qoriq.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 08dbb86..ea1175f 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -53,6 +53,7 @@
 
 enum ahci_qoriq_type {
 	AHCI_LS1021A,
+	AHCI_LS1028A,
 	AHCI_LS1043A,
 	AHCI_LS2080A,
 	AHCI_LS1046A,
@@ -72,6 +73,7 @@ struct ahci_qoriq_priv {
 
 static const struct of_device_id ahci_qoriq_of_match[] = {
 	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
+	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
 	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
 	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
 	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
@@ -223,6 +225,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 		break;
 
+	case AHCI_LS1028A:
 	case AHCI_LS1088A:
 	case AHCI_LX2160A:
 		if (!(qpriv->ecc_addr || ecc_initialized))
-- 
1.7.1

Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list

[Rob Herring]

On Mon, 11 Mar 2019 15:20:12 +0800, Peng Ma wrote:
> Add ls1028a compatible to bindings documentation.
> 
> Signed-off-by: Peng Ma <peng.ma@nxp.com>
> ---
> depends on:
> 	- http://patchwork.ozlabs.org/patch/1045217/
> 
>  .../devicetree/bindings/ata/ahci-fsl-qoriq.txt     |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/3] arm64: dts: ls1028a: Corrected the SATA ecc address.

[Shawn Guo]

On Mon, Mar 11, 2019 at 03:20:13PM +0800, Peng Ma wrote:
> Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the
> address.
> 
> Signed-off-by: Peng Ma <peng.ma@nxp.com>

Applied, thanks.

Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list

[Shawn Guo]

On Mon, Mar 11, 2019 at 03:20:12PM +0800, Peng Ma wrote:
> Add ls1028a compatible to bindings documentation.
> 
> Signed-off-by: Peng Ma <peng.ma@nxp.com>

I assume that the bindings will be picked up by Axboe.  Otherwise,
please let me know.

Shawn

RE: [EXT] Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list

[Peng Ma]

Hi Shawn,

OK, thanks.

Best Regards,
Peng

>-----Original Message-----
>From: Shawn Guo <shawnguo@kernel.org>
>Sent: 2019年4月11日 9:37
>To: Peng Ma <peng.ma@nxp.com>
>Cc: axboe@kernel.dk; robh+dt@kernel.org; mark.rutland@arm.com; Leo Li
><leoyang.li@nxp.com>; linux-ide@vger.kernel.org; devicetree@vger.kernel.org;
>Andy Tang <andy.tang@nxp.com>; linux-kernel@vger.kernel.org;
>linux-arm-kernel@lists.infradead.org
>Subject: [EXT] Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip
>name to the list
>
>WARNING: This email was created outside of NXP. DO NOT CLICK links or
>attachments unless you recognize the sender and know the content is safe.
>
>
>
>On Mon, Mar 11, 2019 at 03:20:12PM +0800, Peng Ma wrote:
>> Add ls1028a compatible to bindings documentation.
>>
>> Signed-off-by: Peng Ma <peng.ma@nxp.com>
>
>I assume that the bindings will be picked up by Axboe.  Otherwise, please let
>me know.
>
>Shawn