* [0/3] TLB flush counters @ 2019-04-10 22:44 Atish Patra 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra ` (2 more replies) 0 siblings, 3 replies; 11+ messages in thread From: Atish Patra @ 2019-04-10 22:44 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Anup Patel, Borislav Petkov, Gary Guo, H. Peter Anvin, Ingo Molnar, linux-riscv, Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) The RISC-V patch (2/3) is based on Gary's TLB flush patch series https://patchwork.kernel.org/project/linux-riscv/list/?series=97315 The x86 kconfig fix patch(1/3) can be applied separately. Atish Patra (3): x86: Update DEBUG_TLBFLUSH options description. RISC-V: Update tlb flush counters RISC-V: Add DEBUG_TLBFLUSH option. arch/riscv/Kconfig.debug | 12 ++++++++++++ arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ arch/x86/Kconfig.debug | 15 +++------------ 4 files changed, 32 insertions(+), 12 deletions(-) -- 2.21.0 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-10 22:44 [0/3] TLB flush counters Atish Patra @ 2019-04-10 22:44 ` Atish Patra 2019-04-11 6:56 ` Christoph Hellwig 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-10 22:44 ` [2/3] RISC-V: Update tlb flush counters Atish Patra 2019-04-10 22:44 ` [3/3] RISC-V: Add DEBUG_TLBFLUSH option Atish Patra 2 siblings, 2 replies; 11+ messages in thread From: Atish Patra @ 2019-04-10 22:44 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Anup Patel, Borislav Petkov, Gary Guo, H. Peter Anvin, Ingo Molnar, linux-riscv, Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) CONFIG_DEBUG_TLBFLUSH was added in 'commit 3df3212f9722 ("x86/tlb: add tlb_flushall_shift knob into debugfs")' to support tlb_flushall_shift knob. The knob was removed in 'commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy TLB flushing")'. However, the debug option was never removed from Kconfig. It was reused in commit '9824cf9753ec ("mm: vmstats: tlb flush counters")' but the commit text was never updated accordingly. Update the Kconfig option description as per its current usage. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/x86/Kconfig.debug | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 15d0fbe27872..c1a48d4ffebb 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -125,21 +125,12 @@ config DOUBLEFAULT hair. config DEBUG_TLBFLUSH - bool "Set upper limit of TLB entries to flush one-by-one" + bool "Save tlb flush statstics to vmstat" depends on DEBUG_KERNEL ---help--- - X86-only for now. - - This option allows the user to tune the amount of TLB entries the - kernel flushes one-by-one instead of doing a full TLB flush. In - certain situations, the former is cheaper. This is controlled by the - tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it - to -1, the code flushes the whole TLB unconditionally. Otherwise, - for positive values of it, the kernel will use single TLB entry - invalidating instructions according to the following formula: - - flush_entries <= active_tlb_entries / 2^tlb_flushall_shift + Add tlbflush statstics to vmstat. It is really helpful understand tlbflush + performance and behavior. It should be enabled only for debugging purpose. If in doubt, say "N". -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra @ 2019-04-11 6:56 ` Christoph Hellwig 2019-04-12 20:14 ` Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 1 sibling, 1 reply; 11+ messages in thread From: Christoph Hellwig @ 2019-04-11 6:56 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Albert Ou, Anup Patel, Borislav Petkov, Gary Guo, H. Peter Anvin, Ingo Molnar, linux-riscv, Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) Given that this option enables generic code (which you reuse for RISC-V later in this series) please also move the config option to mm/Kconfig, proabbly keyed off another ARCH_HAVE_DEBUG_TLBFLUSH symbol that the architecture can select. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-11 6:56 ` Christoph Hellwig @ 2019-04-12 20:14 ` Atish Patra 2019-04-14 14:27 ` Borislav Petkov 0 siblings, 1 reply; 11+ messages in thread From: Atish Patra @ 2019-04-12 20:14 UTC (permalink / raw) To: Christoph Hellwig Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Albert Ou, Anup Patel, Palmer Dabbelt, linux-kernel, Ingo Molnar, Borislav Petkov, Gary Guo, H. Peter Anvin, linux-riscv, Thomas Gleixner, Luc Van Oostenryck On 4/10/19 11:56 PM, Christoph Hellwig wrote: > Given that this option enables generic code (which you reuse for RISC-V > later in this series) please also move the config option to > mm/Kconfig, proabbly keyed off another ARCH_HAVE_DEBUG_TLBFLUSH > symbol that the architecture can select. > Sure. Regards, Atish > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-12 20:14 ` Atish Patra @ 2019-04-14 14:27 ` Borislav Petkov 2019-04-29 19:52 ` Atish Patra 0 siblings, 1 reply; 11+ messages in thread From: Borislav Petkov @ 2019-04-14 14:27 UTC (permalink / raw) To: Atish Patra Cc: Christoph Hellwig, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Albert Ou, Anup Patel, Palmer Dabbelt, linux-kernel, Ingo Molnar, Gary Guo, H. Peter Anvin, linux-riscv, Thomas Gleixner, Luc Van Oostenryck On Fri, Apr 12, 2019 at 01:14:54PM -0700, Atish Patra wrote: > On 4/10/19 11:56 PM, Christoph Hellwig wrote: > > Given that this option enables generic code (which you reuse for RISC-V > > later in this series) please also move the config option to > > mm/Kconfig, proabbly keyed off another ARCH_HAVE_DEBUG_TLBFLUSH > > symbol that the architecture can select. > > > > Sure. And when you do that, instead of deleting the help text, make it generic. Otherwise, there's no explanation anymore, how that option is supposed to be used through tlb_flushall_shift. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-14 14:27 ` Borislav Petkov @ 2019-04-29 19:52 ` Atish Patra 0 siblings, 0 replies; 11+ messages in thread From: Atish Patra @ 2019-04-29 19:52 UTC (permalink / raw) To: Borislav Petkov Cc: Christoph Hellwig, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Albert Ou, Anup Patel, Palmer Dabbelt, linux-kernel, Ingo Molnar, Gary Guo, H. Peter Anvin, linux-riscv, Thomas Gleixner, Luc Van Oostenryck On 4/14/19 7:29 AM, Borislav Petkov wrote: > On Fri, Apr 12, 2019 at 01:14:54PM -0700, Atish Patra wrote: >> On 4/10/19 11:56 PM, Christoph Hellwig wrote: >>> Given that this option enables generic code (which you reuse for RISC-V >>> later in this series) please also move the config option to >>> mm/Kconfig, proabbly keyed off another ARCH_HAVE_DEBUG_TLBFLUSH >>> symbol that the architecture can select. >>> >> >> Sure. > > And when you do that, instead of deleting the help text, make it > generic. Otherwise, there's no explanation anymore, how that option is > supposed to be used through tlb_flushall_shift. > Not sure I am following you. tlb_flushall_shift knob was removed by commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy TLB flushing") Regards, Atish ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [1/3] x86: Update DEBUG_TLBFLUSH options description. 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra 2019-04-11 6:56 ` Christoph Hellwig @ 2019-04-25 20:17 ` Palmer Dabbelt 1 sibling, 0 replies; 11+ messages in thread From: Palmer Dabbelt @ 2019-04-25 20:17 UTC (permalink / raw) To: atish.patra Cc: linux-kernel, atish.patra, aou, anup, bp, gary, hpa, mingo, linux-riscv, luc.vanoostenryck, tglx, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) On Wed, 10 Apr 2019 15:44:47 PDT (-0700), atish.patra@wdc.com wrote: > CONFIG_DEBUG_TLBFLUSH was added in 'commit 3df3212f9722 ("x86/tlb: add > tlb_flushall_shift knob into debugfs")' to support tlb_flushall_shift > knob. The knob was removed in 'commit e9f4e0a9fe27 ("x86/mm: Rip out > complicated, out-of-date, buggy TLB flushing")'. However, the debug > option was never removed from Kconfig. It was reused in commit > '9824cf9753ec ("mm: vmstats: tlb flush counters")' but the commit text was > never updated accordingly. > > Update the Kconfig option description as per its current usage. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/x86/Kconfig.debug | 15 +++------------ > 1 file changed, 3 insertions(+), 12 deletions(-) > > diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug > index 15d0fbe27872..c1a48d4ffebb 100644 > --- a/arch/x86/Kconfig.debug > +++ b/arch/x86/Kconfig.debug > @@ -125,21 +125,12 @@ config DOUBLEFAULT > hair. > > config DEBUG_TLBFLUSH > - bool "Set upper limit of TLB entries to flush one-by-one" > + bool "Save tlb flush statstics to vmstat" > depends on DEBUG_KERNEL > ---help--- > > - X86-only for now. > - > - This option allows the user to tune the amount of TLB entries the > - kernel flushes one-by-one instead of doing a full TLB flush. In > - certain situations, the former is cheaper. This is controlled by the > - tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it > - to -1, the code flushes the whole TLB unconditionally. Otherwise, > - for positive values of it, the kernel will use single TLB entry > - invalidating instructions according to the following formula: > - > - flush_entries <= active_tlb_entries / 2^tlb_flushall_shift > + Add tlbflush statstics to vmstat. It is really helpful understand tlbflush > + performance and behavior. It should be enabled only for debugging purpose. > > If in doubt, say "N". Reviewed-by: Palmer Dabbelt <palmer@sifivee.com> I'm not going to take this via my tree, but I'll look into the next two. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [2/3] RISC-V: Update tlb flush counters 2019-04-10 22:44 [0/3] TLB flush counters Atish Patra 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra @ 2019-04-10 22:44 ` Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-10 22:44 ` [3/3] RISC-V: Add DEBUG_TLBFLUSH option Atish Patra 2 siblings, 1 reply; 11+ messages in thread From: Atish Patra @ 2019-04-10 22:44 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Anup Patel, Borislav Petkov, Gary Guo, H. Peter Anvin, Ingo Molnar, linux-riscv, Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Update the counters in every TLB flush methods respectively. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 29a780ca232a..19779a083f52 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -9,6 +9,7 @@ #define _ASM_RISCV_TLBFLUSH_H #include <linux/mm_types.h> +#include <linux/vmstat.h> /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction @@ -16,11 +17,13 @@ */ static inline void local_flush_tlb_all(void) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); /* Flush ASID 0 so that global mappings are not affected */ __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); } @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (0) : "memory"); @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, static inline void local_flush_tlb_kernel_page(unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ceee76f14a0a..8072d7da32bb 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,6 +4,8 @@ */ #include <linux/mm.h> +#include <linux/vmstat.h> +#include <linux/cpumask.h> #include <asm/sbi.h> #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); if (size == SFENCE_VMA_FLUSH_ALL) { local_flush_tlb_all(); } @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); + /* Flush entire MM context */ if (size == SFENCE_VMA_FLUSH_ALL) { __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, unsigned long size, unsigned long asid) { + int cpuid = smp_processor_id(); + + if (cpumask_equal(mask, cpumask_of(cpuid))) + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); + else + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (tlbi_ipi) { struct tlbi info = { .start = start, -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [2/3] RISC-V: Update tlb flush counters 2019-04-10 22:44 ` [2/3] RISC-V: Update tlb flush counters Atish Patra @ 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-26 18:54 ` Atish Patra 0 siblings, 1 reply; 11+ messages in thread From: Palmer Dabbelt @ 2019-04-25 20:17 UTC (permalink / raw) To: atish.patra Cc: linux-kernel, atish.patra, aou, anup, bp, gary, hpa, mingo, linux-riscv, luc.vanoostenryck, tglx, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) On Wed, 10 Apr 2019 15:44:48 PDT (-0700), atish.patra@wdc.com wrote: > The TLB flush counters under vmstat seems to be very helpful while > debugging TLB flush performance in RISC-V. > > Update the counters in every TLB flush methods respectively. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/include/asm/tlbflush.h | 5 +++++ > arch/riscv/mm/tlbflush.c | 12 ++++++++++++ > 2 files changed, 17 insertions(+) > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index 29a780ca232a..19779a083f52 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -9,6 +9,7 @@ > #define _ASM_RISCV_TLBFLUSH_H > > #include <linux/mm_types.h> > +#include <linux/vmstat.h> > > /* > * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction > @@ -16,11 +17,13 @@ > */ > static inline void local_flush_tlb_all(void) > { > + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > } > > static inline void local_flush_tlb_mm(struct mm_struct *mm) > { > + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); > /* Flush ASID 0 so that global mappings are not affected */ > __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); > } > @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) > static inline void local_flush_tlb_page(struct vm_area_struct *vma, > unsigned long addr) > { > + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); > __asm__ __volatile__ ("sfence.vma %0, %1" > : : "r" (addr), "r" (0) > : "memory"); > @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, > > static inline void local_flush_tlb_kernel_page(unsigned long addr) > { > + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); > __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); > } > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index ceee76f14a0a..8072d7da32bb 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -4,6 +4,8 @@ > */ > > #include <linux/mm.h> > +#include <linux/vmstat.h> > +#include <linux/cpumask.h> > #include <asm/sbi.h> > > #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) > @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) > unsigned long size = data->size; > unsigned long i; > > + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); > if (size == SFENCE_VMA_FLUSH_ALL) { > local_flush_tlb_all(); > } > @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) > unsigned long size = data->size; > unsigned long i; > > + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); > + /* Flush entire MM context */ > if (size == SFENCE_VMA_FLUSH_ALL) { > __asm__ __volatile__ ("sfence.vma x0, %0" > : : "r" (asid) > @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) > static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, > unsigned long size, unsigned long asid) > { > + int cpuid = smp_processor_id(); > + > + if (cpumask_equal(mask, cpumask_of(cpuid))) > + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); > + else > + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); > + > if (tlbi_ipi) { > struct tlbi info = { > .start = start, Looks good, but it's not applying on for-next (based on rc6). Do you mind re-spinning the patches? ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [2/3] RISC-V: Update tlb flush counters 2019-04-25 20:17 ` Palmer Dabbelt @ 2019-04-26 18:54 ` Atish Patra 0 siblings, 0 replies; 11+ messages in thread From: Atish Patra @ 2019-04-26 18:54 UTC (permalink / raw) To: Palmer Dabbelt Cc: aou, anup, maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT, linux-kernel, mingo, bp, gary, hpa, linux-riscv, tglx, luc.vanoostenryck On 4/25/19 10:31 PM, Palmer Dabbelt wrote: > On Wed, 10 Apr 2019 15:44:48 PDT (-0700), atish.patra@wdc.com wrote: >> The TLB flush counters under vmstat seems to be very helpful while >> debugging TLB flush performance in RISC-V. >> >> Update the counters in every TLB flush methods respectively. >> >> Signed-off-by: Atish Patra <atish.patra@wdc.com> >> --- >> arch/riscv/include/asm/tlbflush.h | 5 +++++ >> arch/riscv/mm/tlbflush.c | 12 ++++++++++++ >> 2 files changed, 17 insertions(+) >> >> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h >> index 29a780ca232a..19779a083f52 100644 >> --- a/arch/riscv/include/asm/tlbflush.h >> +++ b/arch/riscv/include/asm/tlbflush.h >> @@ -9,6 +9,7 @@ >> #define _ASM_RISCV_TLBFLUSH_H >> >> #include <linux/mm_types.h> >> +#include <linux/vmstat.h> >> >> /* >> * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction >> @@ -16,11 +17,13 @@ >> */ >> static inline void local_flush_tlb_all(void) >> { >> + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); >> __asm__ __volatile__ ("sfence.vma" : : : "memory"); >> } >> >> static inline void local_flush_tlb_mm(struct mm_struct *mm) >> { >> + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); >> /* Flush ASID 0 so that global mappings are not affected */ >> __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); >> } >> @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) >> static inline void local_flush_tlb_page(struct vm_area_struct *vma, >> unsigned long addr) >> { >> + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); >> __asm__ __volatile__ ("sfence.vma %0, %1" >> : : "r" (addr), "r" (0) >> : "memory"); >> @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, >> >> static inline void local_flush_tlb_kernel_page(unsigned long addr) >> { >> + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); >> __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); >> } >> >> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c >> index ceee76f14a0a..8072d7da32bb 100644 >> --- a/arch/riscv/mm/tlbflush.c >> +++ b/arch/riscv/mm/tlbflush.c >> @@ -4,6 +4,8 @@ >> */ >> >> #include <linux/mm.h> >> +#include <linux/vmstat.h> >> +#include <linux/cpumask.h> >> #include <asm/sbi.h> >> >> #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) >> @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) >> unsigned long size = data->size; >> unsigned long i; >> >> + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); >> if (size == SFENCE_VMA_FLUSH_ALL) { >> local_flush_tlb_all(); >> } >> @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) >> unsigned long size = data->size; >> unsigned long i; >> >> + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); >> + /* Flush entire MM context */ >> if (size == SFENCE_VMA_FLUSH_ALL) { >> __asm__ __volatile__ ("sfence.vma x0, %0" >> : : "r" (asid) >> @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) >> static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, >> unsigned long size, unsigned long asid) >> { >> + int cpuid = smp_processor_id(); >> + >> + if (cpumask_equal(mask, cpumask_of(cpuid))) >> + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); >> + else >> + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); >> + >> if (tlbi_ipi) { >> struct tlbi info = { >> .start = start, > > Looks good, but it's not applying on for-next (based on rc6). Do you mind > re-spinning the patches? > > This patch depends is based on Gary's TLB flush patch series https://patchwork.kernel.org/project/linux-riscv/list/?series=97315 So it should only be merged on top of it. Regards, Atish > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [3/3] RISC-V: Add DEBUG_TLBFLUSH option. 2019-04-10 22:44 [0/3] TLB flush counters Atish Patra 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra 2019-04-10 22:44 ` [2/3] RISC-V: Update tlb flush counters Atish Patra @ 2019-04-10 22:44 ` Atish Patra 2 siblings, 0 replies; 11+ messages in thread From: Atish Patra @ 2019-04-10 22:44 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Anup Patel, Borislav Petkov, Gary Guo, H. Peter Anvin, Ingo Molnar, linux-riscv, Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Add the Kconfig option only for debug kernels. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/Kconfig.debug | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..6a2d3762aeda 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 + +config DEBUG_TLBFLUSH + bool "Save tlb flush statstics to vmstat" + depends on DEBUG_KERNEL + help + + Add TLB flush statstics to vmstat. It is really helpful understand tlbflush + performance and behavior. It should be enabled only for debugging purpose. + + If in doubt, say "N". + -- 2.21.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-04-29 19:52 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-10 22:44 [0/3] TLB flush counters Atish Patra 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra 2019-04-11 6:56 ` Christoph Hellwig 2019-04-12 20:14 ` Atish Patra 2019-04-14 14:27 ` Borislav Petkov 2019-04-29 19:52 ` Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-10 22:44 ` [2/3] RISC-V: Update tlb flush counters Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-26 18:54 ` Atish Patra 2019-04-10 22:44 ` [3/3] RISC-V: Add DEBUG_TLBFLUSH option Atish Patra
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).