From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: mingo@redhat.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, acme@kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com
Subject: Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support
Date: Thu, 11 Apr 2019 11:06:58 +0200 [thread overview]
Message-ID: <20190411090658.GD4038@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1554922629-126287-3-git-send-email-kan.liang@linux.intel.com>
On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.liang@linux.intel.com wrote:
> +static struct event_constraint *
> +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> + struct perf_event *event)
That 'tnt' still cracks me up, I keep seeing explosions.
> +{
> + struct event_constraint *c;
> +
> + /*
> + * :ppp means to do reduced skid PEBS,
> + * which is available on PMC0 and fixed counter 0.
> + */
> + if (event->attr.precise_ip == 3) {
> + /* Force instruction:ppp on PMC0 and Fixed counter 0 */
> + if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))
> + return &fixed0_counter0_constraint;
> +
> + return &counter0_constraint;
> + }
> +
> + c = intel_get_event_constraints(cpuc, idx, event);
> +
> + return c;
> +}
I changed that like so:
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_
*/
if (event->attr.precise_ip == 3) {
/* Force instruction:ppp on PMC0 and Fixed counter 0 */
- if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))
+ if (constraint_match(&fixed_counter0_constraint, event->hw.config))
return &fixed0_counter0_constraint;
return &counter0_constraint;
And maybe we should do:
s/fixed_counter0_constraint/fixed0_constraint/'
Those two constraints only differ by a single character, that's bad for
reading comprehension.
In fact, I just did that too.
next prev parent reply other threads:[~2019-04-11 9:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang
2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang
2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang
2019-04-11 9:06 ` Peter Zijlstra [this message]
2019-04-11 13:30 ` Liang, Kan
2019-04-11 13:33 ` Peter Zijlstra
2019-04-11 14:13 ` Liang, Kan
2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang
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