From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: mingo@redhat.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, acme@kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com
Subject: Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support
Date: Thu, 11 Apr 2019 15:33:31 +0200 [thread overview]
Message-ID: <20190411133331.GE11158@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <9ef797ad-bce6-2883-8245-20bdf0b79142@linux.intel.com>
On Thu, Apr 11, 2019 at 09:30:10AM -0400, Liang, Kan wrote:
> > I changed that like so:
> >
> > --- a/arch/x86/events/intel/core.c
> > +++ b/arch/x86/events/intel/core.c
> > @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_
> > */
> > if (event->attr.precise_ip == 3) {
> > /* Force instruction:ppp on PMC0 and Fixed counter 0 */
> > - if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))
> > + if (constraint_match(&fixed_counter0_constraint, event->hw.config))
>
> Should be
> if (constraint_match(&fixed0_counter0_constraint, event->hw.config))
No, because fixed0_counter0_constraint doesn't set an event.
The logic as I proposed checks if it fits the fixed0 constraint, and if
so, allows f0-c0, otherwise only c0.
> > return &fixed0_counter0_constraint;
> > return &counter0_constraint;
> >
next prev parent reply other threads:[~2019-04-11 13:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang
2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang
2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang
2019-04-11 9:06 ` Peter Zijlstra
2019-04-11 13:30 ` Liang, Kan
2019-04-11 13:33 ` Peter Zijlstra [this message]
2019-04-11 14:13 ` Liang, Kan
2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang
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