* [PATCH 0/3] Allow accessing CSR using CSR number
@ 2019-04-13 7:39 Anup Patel
2019-04-13 7:39 ` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Anup Patel @ 2019-04-13 7:39 UTC (permalink / raw)
To: Palmer Dabbelt, Albert Ou
Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv,
linux-kernel, Anup Patel
This patch series adds support to access CSR using both CSR name and
CSR numbers.
Also, we should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.)
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.)
The patchset can be found in riscv_csr_number_v1 branch of
https//github.com/avpatel/linux.git
Anup Patel (3):
RISC-V: Add separate asm/encoding.h for spec related defines
RISC-V: Add defines for CSR numbers
RISC-V: Access CSRs using CSR numbers
arch/riscv/include/asm/csr.h | 67 +-----
arch/riscv/include/asm/encoding.h | 299 +++++++++++++++++++++++++++
arch/riscv/include/asm/irqflags.h | 10 +-
arch/riscv/include/asm/mmu_context.h | 2 +-
arch/riscv/kernel/entry.S | 22 +-
arch/riscv/kernel/head.S | 12 +-
arch/riscv/kernel/perf_event.c | 4 +-
arch/riscv/kernel/smp.c | 2 +-
arch/riscv/kernel/traps.c | 6 +-
arch/riscv/mm/fault.c | 2 +-
10 files changed, 338 insertions(+), 88 deletions(-)
create mode 100644 arch/riscv/include/asm/encoding.h
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines 2019-04-13 7:39 [PATCH 0/3] Allow accessing CSR using CSR number Anup Patel @ 2019-04-13 7:39 ` Anup Patel 2019-04-13 7:53 ` Christoph Hellwig 2019-04-13 7:39 ` [PATCH 2/3] RISC-V: Add defines for CSR numbers Anup Patel 2019-04-13 7:39 ` [PATCH 3/3] RISC-V: Access CSRs using " Anup Patel 2 siblings, 1 reply; 10+ messages in thread From: Anup Patel @ 2019-04-13 7:39 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel It's better to have all RISC-V spec related defines in one place so this patch adds separate asm/encoding.h for such defines which can be included in assembly as well as C code. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 52 +------------------------- arch/riscv/include/asm/encoding.h | 62 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 51 deletions(-) create mode 100644 arch/riscv/include/asm/encoding.h diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 28a0d1cb374c..8cf698e39463 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,57 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H -#include <linux/const.h> - -/* Status register flags */ -#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ -#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ -#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ -#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ - -#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ -#define SR_FS_OFF _AC(0x00000000, UL) -#define SR_FS_INITIAL _AC(0x00002000, UL) -#define SR_FS_CLEAN _AC(0x00004000, UL) -#define SR_FS_DIRTY _AC(0x00006000, UL) - -#define SR_XS _AC(0x00018000, UL) /* Extension Status */ -#define SR_XS_OFF _AC(0x00000000, UL) -#define SR_XS_INITIAL _AC(0x00008000, UL) -#define SR_XS_CLEAN _AC(0x00010000, UL) -#define SR_XS_DIRTY _AC(0x00018000, UL) - -#ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ -#else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ -#endif - -/* SATP flags */ -#if __riscv_xlen == 32 -#define SATP_PPN _AC(0x003FFFFF, UL) -#define SATP_MODE_32 _AC(0x80000000, UL) -#define SATP_MODE SATP_MODE_32 -#else -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE SATP_MODE_39 -#endif - -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ - -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 +#include <asm/encoding.h> #ifndef __ASSEMBLY__ diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h new file mode 100644 index 000000000000..8d8bf424847b --- /dev/null +++ b/arch/riscv/include/asm/encoding.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Regents of the University of California + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_ENCODING_H +#define _ASM_RISCV_ENCODING_H + +#include <linux/const.h> + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif + +/* SATP flags */ +#if __riscv_xlen == 32 +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif + +/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ +#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 + +#endif /* _ASM_RISCV_CSR_H */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines 2019-04-13 7:39 ` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel @ 2019-04-13 7:53 ` Christoph Hellwig 2019-04-13 8:14 ` Anup Patel 0 siblings, 1 reply; 10+ messages in thread From: Christoph Hellwig @ 2019-04-13 7:53 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Sat, Apr 13, 2019 at 07:39:35AM +0000, Anup Patel wrote: > It's better to have all RISC-V spec related defines in one place > so this patch adds separate asm/encoding.h for such defines which > can be included in assembly as well as C code. <asm/csr.h> can be included from assembly just fine already. and we already do that. So I don't really see much of a point in splitting it. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines 2019-04-13 7:53 ` Christoph Hellwig @ 2019-04-13 8:14 ` Anup Patel 0 siblings, 0 replies; 10+ messages in thread From: Anup Patel @ 2019-04-13 8:14 UTC (permalink / raw) To: Christoph Hellwig Cc: Anup Patel, Palmer Dabbelt, Albert Ou, linux-kernel, Atish Patra, Paul Walmsley, linux-riscv On Sat, Apr 13, 2019 at 1:23 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Sat, Apr 13, 2019 at 07:39:35AM +0000, Anup Patel wrote: > > It's better to have all RISC-V spec related defines in one place > > so this patch adds separate asm/encoding.h for such defines which > > can be included in assembly as well as C code. > > <asm/csr.h> can be included from assembly just fine already. > and we already do that. So I don't really see much of a point > in splitting it. We would be also having #defines which will help us decode load/store instructions as well. This will be used for load/store emulation for MMIO devices in KVM hypervisor. Consider this patch as preparatory patch for the KVM support we are working on. Regards, Anup ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] RISC-V: Add defines for CSR numbers 2019-04-13 7:39 [PATCH 0/3] Allow accessing CSR using CSR number Anup Patel 2019-04-13 7:39 ` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel @ 2019-04-13 7:39 ` Anup Patel 2019-04-13 7:54 ` Christoph Hellwig 2019-04-13 7:39 ` [PATCH 3/3] RISC-V: Access CSRs using " Anup Patel 2 siblings, 1 reply; 10+ messages in thread From: Anup Patel @ 2019-04-13 7:39 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel Each CSR is encoded as 12bit number in RISC-V instructions. This patch adds defines for CSR numbers to allow us access CSRs using CSR numbers. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/encoding.h | 237 ++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 8d8bf424847b..430e00a8edd0 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -49,6 +49,243 @@ #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ #define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ +#define CSR_USTATUS 0x0 +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_UIE 0x4 +#define CSR_UTVEC 0x5 +#define CSR_USCRATCH 0x40 +#define CSR_UEPC 0x41 +#define CSR_UCAUSE 0x42 +#define CSR_UTVAL 0x43 +#define CSR_UIP 0x44 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 + +#define CSR_BSSTATUS 0x200 +#define CSR_BSIE 0x204 +#define CSR_BSTVEC 0x205 +#define CSR_BSSCRATCH 0x240 +#define CSR_BSEPC 0x241 +#define CSR_BSCAUSE 0x242 +#define CSR_BSTVAL 0x243 +#define CSR_BSIP 0x244 +#define CSR_BSATP 0x280 + +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 + +#define CSR_HSTATUS 0xa00 +#define CSR_HEDELEG 0xa02 +#define CSR_HIDELEG 0xa03 +#define CSR_HGATP 0xa80 + +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 #define EXC_BREAKPOINT 3 -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] RISC-V: Add defines for CSR numbers 2019-04-13 7:39 ` [PATCH 2/3] RISC-V: Add defines for CSR numbers Anup Patel @ 2019-04-13 7:54 ` Christoph Hellwig 2019-04-13 8:14 ` Anup Patel 0 siblings, 1 reply; 10+ messages in thread From: Christoph Hellwig @ 2019-04-13 7:54 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv I think this should be merged with the next patch. Also please only add the CSRs that we actually use. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] RISC-V: Add defines for CSR numbers 2019-04-13 7:54 ` Christoph Hellwig @ 2019-04-13 8:14 ` Anup Patel 0 siblings, 0 replies; 10+ messages in thread From: Anup Patel @ 2019-04-13 8:14 UTC (permalink / raw) To: Christoph Hellwig Cc: Anup Patel, Palmer Dabbelt, Albert Ou, linux-kernel, Atish Patra, Paul Walmsley, linux-riscv On Sat, Apr 13, 2019 at 1:24 PM Christoph Hellwig <hch@infradead.org> wrote: > > I think this should be merged with the next patch. Also please > only add the CSRs that we actually use. Sure, will do. Regards, Anup ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] RISC-V: Access CSRs using CSR numbers 2019-04-13 7:39 [PATCH 0/3] Allow accessing CSR using CSR number Anup Patel 2019-04-13 7:39 ` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel 2019-04-13 7:39 ` [PATCH 2/3] RISC-V: Add defines for CSR numbers Anup Patel @ 2019-04-13 7:39 ` Anup Patel 2019-04-13 7:55 ` Christoph Hellwig 2 siblings, 1 reply; 10+ messages in thread From: Anup Patel @ 2019-04-13 7:39 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 15 ++++++++------- arch/riscv/include/asm/irqflags.h | 10 +++++----- arch/riscv/include/asm/mmu_context.h | 2 +- arch/riscv/kernel/entry.S | 22 +++++++++++----------- arch/riscv/kernel/head.S | 12 ++++++------ arch/riscv/kernel/perf_event.c | 4 ++-- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +++--- arch/riscv/mm/fault.c | 2 +- 9 files changed, 38 insertions(+), 37 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 8cf698e39463..6bf5652d3565 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,6 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include <asm/asm.h> #include <asm/encoding.h> #ifndef __ASSEMBLY__ @@ -21,7 +22,7 @@ #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -30,7 +31,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -39,7 +40,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -47,7 +48,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -56,7 +57,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -64,7 +65,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -73,7 +74,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 07a3c6d5706f..1a69b3bcd371 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -21,25 +21,25 @@ /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { - return csr_read(sstatus); + return csr_read(CSR_SSTATUS); } /* unconditionally enable interrupts */ static inline void arch_local_irq_enable(void) { - csr_set(sstatus, SR_SIE); + csr_set(CSR_SSTATUS, SR_SIE); } /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(sstatus, SR_SIE); + csr_clear(CSR_SSTATUS, SR_SIE); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(sstatus, SR_SIE); + return csr_read_clear(CSR_SSTATUS, SR_SIE); } /* test flags */ @@ -57,7 +57,7 @@ static inline int arch_irqs_disabled(void) /* set interrupt enabled status */ static inline void arch_local_irq_restore(unsigned long flags) { - csr_set(sstatus, flags & SR_SIE); + csr_set(CSR_SSTATUS, flags & SR_SIE); } #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 336d60ec5698..42094c3f80d6 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -88,7 +88,7 @@ static inline void switch_mm(struct mm_struct *prev, * name to support binutils 2.29 which doesn't know about the * privileged ISA 1.10 yet. */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index fd9b57c8b4ce..1c1ecc238cfa 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -37,11 +37,11 @@ * the kernel thread pointer. If we came from the kernel, sscratch * will contain 0, and we should continue on the current TP. */ - csrrw tp, sscratch, tp + csrrw tp, CSR_SSCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: - csrr tp, sscratch + csrr tp, CSR_SSCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) _save_context: REG_S sp, TASK_TI_USER_SP(tp) @@ -87,11 +87,11 @@ _save_context: li t0, SR_SUM | SR_FS REG_L s0, TASK_TI_USER_SP(tp) - csrrc s1, sstatus, t0 - csrr s2, sepc - csrr s3, sbadaddr - csrr s4, scause - csrr s5, sscratch + csrrc s1, CSR_SSTATUS, t0 + csrr s2, CSR_SEPC + csrr s3, CSR_STVAL + csrr s4, CSR_SCAUSE + csrr s5, CSR_SSCRATCH REG_S s0, PT_SP(sp) REG_S s1, PT_SSTATUS(sp) REG_S s2, PT_SEPC(sp) @@ -107,8 +107,8 @@ _save_context: .macro RESTORE_ALL REG_L a0, PT_SSTATUS(sp) REG_L a2, PT_SEPC(sp) - csrw sstatus, a0 - csrw sepc, a2 + csrw CSR_SSTATUS, a0 + csrw CSR_SEPC, a2 REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) @@ -155,7 +155,7 @@ ENTRY(handle_exception) * Set sscratch register to 0, so that if a recursive exception * occurs, the exception vector knows it came from the kernel */ - csrw sscratch, x0 + csrw CSR_SSCRATCH, x0 /* Load the global pointer */ .option push @@ -248,7 +248,7 @@ resume_userspace: * Save TP into sscratch, so we can find the kernel data structures * again. */ - csrw sscratch, tp + csrw CSR_SSCRATCH, tp restore_all: RESTORE_ALL diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fe884cd69abd..041492636b45 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -23,7 +23,7 @@ __INIT ENTRY(_start) /* Mask all interrupts */ - csrw sie, zero + csrw CSR_SIE, zero /* Load the global pointer */ .option push @@ -89,7 +89,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -105,12 +105,12 @@ relocate: srl a0, a0, PAGE_SHIFT or a0, a0, a1 sfence.vma - csrw sptbr, a0 + csrw CSR_SATP, a0 .align 2 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Reload the global pointer */ .option push @@ -119,7 +119,7 @@ relocate: .option pop /* Switch to kernel page tables */ - csrw sptbr, a2 + csrw CSR_SATP, a2 ret @@ -130,7 +130,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw stvec, a3 + csrw CSR_STVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea..91626d9ae5f2 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -185,10 +185,10 @@ static inline u64 read_counter(int idx) switch (idx) { case RISCV_PMU_CYCLE: - val = csr_read(cycle); + val = csr_read(CSR_CYCLE); break; case RISCV_PMU_INSTRET: - val = csr_read(instret); + val = csr_read(CSR_INSTRET); break; default: WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 0c41d07ec281..f244c63d29e4 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,7 +89,7 @@ void riscv_software_interrupt(void) unsigned long *stats = ipi_data[smp_processor_id()].stats; /* Clear pending IPI */ - csr_clear(sip, SIE_SSIE); + csr_clear(CSR_SIP, SIE_SSIE); while (true) { unsigned long ops; diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 24a9333dda2c..1b407a9db3fc 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -159,9 +159,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(sscratch, 0); + csr_write(CSR_SSCRATCH, 0); /* Set the exception vector address */ - csr_write(stvec, &handle_exception); + csr_write(CSR_STVEC, &handle_exception); /* Enable all interrupts */ - csr_write(sie, -1); + csr_write(CSR_SIE, -1); } diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 88401d5125bc..bb0461ed7efc 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -245,7 +245,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs) * the privileged ISA 1.10 yet. */ index = pgd_index(addr); - pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index; + pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index; pgd_k = init_mm.pgd + index; if (!pgd_present(*pgd_k)) -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] RISC-V: Access CSRs using CSR numbers 2019-04-13 7:39 ` [PATCH 3/3] RISC-V: Access CSRs using " Anup Patel @ 2019-04-13 7:55 ` Christoph Hellwig 2019-04-13 8:15 ` Anup Patel 0 siblings, 1 reply; 10+ messages in thread From: Christoph Hellwig @ 2019-04-13 7:55 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Sat, Apr 13, 2019 at 07:39:44AM +0000, Anup Patel wrote: > We should prefer accessing CSRs using their CSR numbers because: > 1. It compiles fine with older toolchains. > 2. We can use latest CSR names in #define macro names of CSR numbers > as-per RISC-V spec. > 3. We can access newly added CSRs even if toolchain does not recognize > newly addes CSRs by name. This looks mostly fine, but also please remove all the comments regarding using sptbr instead of satp now that they are not true anymore. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] RISC-V: Access CSRs using CSR numbers 2019-04-13 7:55 ` Christoph Hellwig @ 2019-04-13 8:15 ` Anup Patel 0 siblings, 0 replies; 10+ messages in thread From: Anup Patel @ 2019-04-13 8:15 UTC (permalink / raw) To: Christoph Hellwig Cc: Anup Patel, Palmer Dabbelt, Albert Ou, linux-kernel, Atish Patra, Paul Walmsley, linux-riscv On Sat, Apr 13, 2019 at 1:25 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Sat, Apr 13, 2019 at 07:39:44AM +0000, Anup Patel wrote: > > We should prefer accessing CSRs using their CSR numbers because: > > 1. It compiles fine with older toolchains. > > 2. We can use latest CSR names in #define macro names of CSR numbers > > as-per RISC-V spec. > > 3. We can access newly added CSRs even if toolchain does not recognize > > newly addes CSRs by name. > > This looks mostly fine, but also please remove all the comments > regarding using sptbr instead of satp now that they are not true > anymore. Sure, will do. Regards, Anup ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-04-13 8:15 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-13 7:39 [PATCH 0/3] Allow accessing CSR using CSR number Anup Patel 2019-04-13 7:39 ` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel 2019-04-13 7:53 ` Christoph Hellwig 2019-04-13 8:14 ` Anup Patel 2019-04-13 7:39 ` [PATCH 2/3] RISC-V: Add defines for CSR numbers Anup Patel 2019-04-13 7:54 ` Christoph Hellwig 2019-04-13 8:14 ` Anup Patel 2019-04-13 7:39 ` [PATCH 3/3] RISC-V: Access CSRs using " Anup Patel 2019-04-13 7:55 ` Christoph Hellwig 2019-04-13 8:15 ` Anup Patel
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).