From: Rob Herring <robh@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
mark.rutland@arm.com, thierry.reding@gmail.com,
jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com,
will.deacon@arm.com, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V5 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block
Date: Fri, 26 Apr 2019 10:45:19 -0500 [thread overview]
Message-ID: <20190426154519.GA19329@bogus> (raw)
In-Reply-To: <20190424052004.6270-12-vidyas@nvidia.com>
On Wed, Apr 24, 2019 at 10:49:59AM +0530, Vidya Sagar wrote:
> Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
> module instantiated one for each PCIe lane between Synopsys Designware core
> based PCIe IP and Universal PHY block.
Missing Sob.
> ---
> Changes since [v4]:
> * None
>
> Changes since [v3]:
> * None
>
> Changes since [v2]:
> * Changed node label to reflect new format that includes either 'hsio' or
> 'nvhs' in its name to reflect which UPHY brick they belong to
>
> Changes since [v1]:
> * This is a new patch in v2 series
>
> .../bindings/phy/phy-tegra194-p2u.txt | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
> new file mode 100644
> index 000000000000..8b543cba483b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
> @@ -0,0 +1,28 @@
> +NVIDIA Tegra194 P2U binding
> +
> +Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
> +Speed) each interfacing with 12 and 8 P2U instances respectively.
> +A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
> +interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
> +lane.
> +
> +Required properties:
> +- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
> +- reg: Should be the physical address space and length of respective each P2U
> + instance.
> +- reg-names: Must include the entry "ctl".
-names is pointless when there is only 1.
> +
> +Required properties for PHY port node:
> +- #phy-cells: Defined by generic PHY bindings. Must be 0.
> +
> +Refer to phy/phy-bindings.txt for the generic PHY binding properties.
> +
> +Example:
> +
> +p2u_hsio_0: p2u@3e10000 {
phy@...
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> +};
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-04-26 15:45 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 5:19 [PATCH V5 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-05-03 11:01 ` Thierry Reding
2019-05-07 7:10 ` Vidya Sagar
2019-05-07 7:51 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-05-03 11:07 ` Thierry Reding
2019-05-10 6:21 ` Vidya Sagar
2019-05-10 16:46 ` Bjorn Helgaas
2019-05-10 17:50 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-03 11:13 ` Thierry Reding
2019-05-07 7:49 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-24 8:13 ` Gustavo Pimentel
2019-05-07 8:04 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-26 14:32 ` Rob Herring
2019-05-07 8:25 ` Vidya Sagar
2019-05-13 15:15 ` Rob Herring
2019-05-14 5:29 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-26 15:22 ` Rob Herring
2019-05-07 8:31 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-26 15:43 ` Rob Herring
2019-05-07 9:20 ` Vidya Sagar
2019-05-13 15:20 ` Rob Herring
2019-05-14 6:25 ` Vidya Sagar
2019-05-03 11:19 ` Thierry Reding
2019-05-07 9:26 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-26 15:45 ` Rob Herring [this message]
2019-04-26 16:07 ` Thierry Reding
2019-04-26 18:05 ` Rob Herring
2019-05-07 9:57 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-03 11:26 ` Thierry Reding
2019-05-07 10:10 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-03 11:27 ` Thierry Reding
2019-05-07 10:11 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-03 11:35 ` Thierry Reding
2019-05-07 10:25 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-03 13:08 ` Thierry Reding
2019-05-07 13:54 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
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