* [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe
@ 2019-05-08 22:43 Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller Bjorn Andersson
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Bjorn Andersson @ 2019-05-08 22:43 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
This series defines the PCIe PHY and controller on QCS404 and enable them for
EVB. This was 1 commit, but per Vinod's request its split up in its individual
pieces.
Bjorn Andersson (3):
arm64: dts: qcom: qcs404: Make gcc as reset-controller
arm64: dts: qcom: qcs404: Add PCIe related nodes
arm64: dts: qcom: qcs404-evb: Enable PCIe
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 26 ++++++++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 66 ++++++++++++++++++++++++
2 files changed, 92 insertions(+)
--
2.18.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller
2019-05-08 22:43 [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe Bjorn Andersson
@ 2019-05-08 22:43 ` Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 2/3] arm64: dts: qcom: qcs404: Add PCIe related nodes Bjorn Andersson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2019-05-08 22:43 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
GCC is a reset-controller, so define #reset-cells.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v3:
- Split single patch, no functional change
arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ffedf9640af7..65a2cbeb28be 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -383,6 +383,7 @@
compatible = "qcom,gcc-qcs404";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
assigned-clock-rates = <19200000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/3] arm64: dts: qcom: qcs404: Add PCIe related nodes
2019-05-08 22:43 [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller Bjorn Andersson
@ 2019-05-08 22:43 ` Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 3/3] arm64: dts: qcom: qcs404-evb: Enable PCIe Bjorn Andersson
2019-05-09 12:29 ` [PATCH v4 0/3] arm64: dts: qcom: qcs404: " Vinod Koul
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2019-05-08 22:43 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these
to for the platform.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v3:
- Split single patch, no functional change
arch/arm64/boot/dts/qcom/qcs404.dtsi | 65 ++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 65a2cbeb28be..f97e9c96b7f7 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -412,6 +412,21 @@
#interrupt-cells = <4>;
};
+ pcie_phy: phy@7786000 {
+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+ reg = <0x07786000 0xb8>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
+ reset-names = "phy", "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
sdcc1: sdcc@7804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
@@ -797,6 +812,56 @@
status = "disabled";
};
};
+
+ pcie: pci@10000000 {
+ compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x07780000 0x2000>,
+ <0x10001000 0x2000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
+ <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "iface", "aux", "master_bus", "slave_bus";
+
+ resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb";
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
};
timer {
--
2.18.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 3/3] arm64: dts: qcom: qcs404-evb: Enable PCIe
2019-05-08 22:43 [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 2/3] arm64: dts: qcom: qcs404: Add PCIe related nodes Bjorn Andersson
@ 2019-05-08 22:43 ` Bjorn Andersson
2019-05-09 12:29 ` [PATCH v4 0/3] arm64: dts: qcom: qcs404: " Vinod Koul
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2019-05-08 22:43 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
Enable the PCIe PHY and controller found on the QCS404 EVB.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v3:
- Split single patch, no functional change
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 2c3127167e3c..d1108a6abd0a 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
+#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
@@ -68,6 +69,22 @@
};
};
+&pcie {
+ status = "ok";
+
+ perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&perst_state>;
+};
+
+&pcie_phy {
+ status = "ok";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+};
+
&remoteproc_adsp {
status = "ok";
};
@@ -184,6 +201,15 @@
};
&tlmm {
+ perst_state: perst {
+ pins = "gpio43";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
--
2.18.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe
2019-05-08 22:43 [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe Bjorn Andersson
` (2 preceding siblings ...)
2019-05-08 22:43 ` [PATCH v4 3/3] arm64: dts: qcom: qcs404-evb: Enable PCIe Bjorn Andersson
@ 2019-05-09 12:29 ` Vinod Koul
3 siblings, 0 replies; 5+ messages in thread
From: Vinod Koul @ 2019-05-09 12:29 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, devicetree, linux-kernel
On 08-05-19, 15:43, Bjorn Andersson wrote:
> This series defines the PCIe PHY and controller on QCS404 and enable them for
> EVB. This was 1 commit, but per Vinod's request its split up in its individual
> pieces.
Thanks for doing that, all:
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-05-09 12:29 UTC | newest]
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2019-05-08 22:43 [PATCH v4 0/3] arm64: dts: qcom: qcs404: Enable PCIe Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 2/3] arm64: dts: qcom: qcs404: Add PCIe related nodes Bjorn Andersson
2019-05-08 22:43 ` [PATCH v4 3/3] arm64: dts: qcom: qcs404-evb: Enable PCIe Bjorn Andersson
2019-05-09 12:29 ` [PATCH v4 0/3] arm64: dts: qcom: qcs404: " Vinod Koul
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