[PATCH 0/3] drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK

[PATCH 0/3] drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK

[james qian wang (Arm Technology China)]

Current komeda driver uses three dedicated clks for a specific purpose:
- mclk: main engine clock
- pclk: APB clock
- pipeline->aclk: AXI clock.

But per spec the komeda HW only has three input clks:
- ACLK: used for AXI masters, APB slave and most pipeline processing
- PXCLK for pipeline 0: output pixel clock for pipeline 0
- PXCLK for pipeline 1: output pixel clock for pipeline 1

So one ACLK is enough, no need to split it to three mclk/pclk/axiclk.

Depends on:
- https://patchwork.freedesktop.org/series/58710/
- https://patchwork.freedesktop.org/series/59000/
- https://patchwork.freedesktop.org/series/59002/
- https://patchwork.freedesktop.org/series/59747/
- https://patchwork.freedesktop.org/series/59915/
- https://patchwork.freedesktop.org/series/60083/
- https://patchwork.freedesktop.org/series/60698/
- https://patchwork.freedesktop.org/series/60856/
- https://patchwork.freedesktop.org/series/60893/
- https://patchwork.freedesktop.org/series/61370/
- https://patchwork.freedesktop.org/series/61379/

James Qian Wang (Arm Technology China) (3):
  drm/komeda: Unify mclk/pclk/pipeline->aclk to one MCLK
  drm/komeda: Rename main engine clk name "mclk" to "aclk"
  dt/bindings: drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK

 .../bindings/display/arm,komeda.txt           | 16 +++----
 .../arm/display/komeda/d71/d71_component.c    | 10 ++---
 .../gpu/drm/arm/display/komeda/komeda_crtc.c  | 45 +++++++------------
 .../gpu/drm/arm/display/komeda/komeda_dev.c   | 39 +++++-----------
 .../gpu/drm/arm/display/komeda/komeda_dev.h   |  6 +--
 .../gpu/drm/arm/display/komeda/komeda_kms.h   |  6 +--
 .../drm/arm/display/komeda/komeda_pipeline.c  |  1 -
 .../drm/arm/display/komeda/komeda_pipeline.h  |  6 +--
 .../display/komeda/komeda_pipeline_state.c    |  4 +-
 9 files changed, 48 insertions(+), 85 deletions(-)

--
2.17.1

[PATCH 1/3] drm/komeda: Unify mclk/pclk/pipeline->aclk to one MCLK

[james qian wang (Arm Technology China)]

Current komeda driver uses three dedicated clks for a specific purpose:
- mclk: main engine clock
- pclk: APB clock
- pipeline->aclk: AXI clock.

But per spec the komeda HW only has three input clks:
- ACLK: used for AXI masters, APB slave and most pipeline processing
- PXCLK for pipeline 0: output pixel clock for pipeline 0
- PXCLK for pipeline 1: output pixel clock for pipeline 1

So one ACLK is enough, no need to split it to three mclk/pclk/axiclk.
drop pclk/pipeline->axiclk. but only keep one mclk in komeda driver.

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
---
 .../gpu/drm/arm/display/komeda/komeda_crtc.c  | 11 -------
 .../gpu/drm/arm/display/komeda/komeda_dev.c   | 33 ++++---------------
 .../gpu/drm/arm/display/komeda/komeda_dev.h   |  2 --
 .../drm/arm/display/komeda/komeda_pipeline.c  |  1 -
 .../drm/arm/display/komeda/komeda_pipeline.h  |  2 --
 5 files changed, 7 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index b5190a1f75eb..3933f4377cc1 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -127,9 +127,6 @@ komeda_crtc_prepare(struct komeda_crtc *kcrtc)
 			DRM_ERROR("failed to enable mclk.\n");
 	}

-	err = clk_prepare_enable(master->aclk);
-	if (err)
-		DRM_ERROR("failed to enable axi clk for pipe%d.\n", master->id);
 	err = clk_set_rate(master->pxlclk, pxlclk_rate);
 	if (err)
 		DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id);
@@ -170,7 +167,6 @@ komeda_crtc_unprepare(struct komeda_crtc *kcrtc)
 	mdev->dpmode = new_mode;

 	clk_disable_unprepare(master->pxlclk);
-	clk_disable_unprepare(master->aclk);
 	if (new_mode == KOMEDA_MODE_INACTIVE)
 		clk_disable_unprepare(mdev->mclk);

@@ -374,13 +370,6 @@ komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
 		return MODE_CLOCK_HIGH;
 	}

-	if (clk_round_rate(master->aclk, mode_clk) < pxlclk) {
-		DRM_DEBUG_ATOMIC("aclk can't satisfy the requirement of %s-clk: %ld.\n",
-				 m->name, pxlclk);
-
-		return MODE_CLOCK_HIGH;
-	}
-
 	return MODE_OK;
 }

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
index 485d8bd12e39..f8f6edbf6f0d 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
@@ -115,13 +115,6 @@ static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)

 	pipe = mdev->pipelines[pipe_id];

-	clk = of_clk_get_by_name(np, "aclk");
-	if (IS_ERR(clk)) {
-		DRM_ERROR("get aclk for pipeline %d failed!\n", pipe_id);
-		return PTR_ERR(clk);
-	}
-	pipe->aclk = clk;
-
 	clk = of_clk_get_by_name(np, "pxclk");
 	if (IS_ERR(clk)) {
 		DRM_ERROR("get pxclk for pipeline %d failed!\n", pipe_id);
@@ -144,14 +137,8 @@ static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct device_node *child, *np = dev->of_node;
-	struct clk *clk;
 	int ret;

-	clk = devm_clk_get(dev, "mclk");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	mdev->mclk = clk;
 	mdev->irq  = platform_get_irq(pdev, 0);
 	if (mdev->irq < 0) {
 		DRM_ERROR("could not get IRQ number.\n");
@@ -205,16 +192,15 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
 		goto err_cleanup;
 	}

-	mdev->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(mdev->pclk)) {
-		DRM_ERROR("Get APB clk failed.\n");
-		err = PTR_ERR(mdev->pclk);
-		mdev->pclk = NULL;
+	mdev->mclk = devm_clk_get(dev, "mclk");
+	if (IS_ERR(mdev->mclk)) {
+		DRM_ERROR("Get engine clk failed.\n");
+		err = PTR_ERR(mdev->mclk);
+		mdev->mclk = NULL;
 		goto err_cleanup;
 	}

-	/* Enable APB clock to access the registers */
-	clk_prepare_enable(mdev->pclk);
+	clk_prepare_enable(mdev->mclk);

 	mdev->funcs = product->identify(mdev->reg_base, &mdev->chip);
 	if (!komeda_product_match(mdev, product->product_id)) {
@@ -315,15 +301,10 @@ void komeda_dev_destroy(struct komeda_dev *mdev)
 	}

 	if (mdev->mclk) {
+		clk_disable_unprepare(mdev->mclk);
 		devm_clk_put(dev, mdev->mclk);
 		mdev->mclk = NULL;
 	}

-	if (mdev->pclk) {
-		clk_disable_unprepare(mdev->pclk);
-		devm_clk_put(dev, mdev->pclk);
-		mdev->pclk = NULL;
-	}
-
 	devm_kfree(dev, mdev);
 }
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
index 5126879d597e..5feaed2dc93f 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
@@ -160,8 +160,6 @@ struct komeda_dev {
 	struct komeda_chip_info chip;
 	/** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
 	struct komeda_format_caps_table fmt_tbl;
-	/** @pclk: APB clock for register access */
-	struct clk *pclk;
 	/** @mclk: HW main engine clk */
 	struct clk *mclk;

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
index 0bb443b336f7..78e44d9e1520 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
@@ -53,7 +53,6 @@ void komeda_pipeline_destroy(struct komeda_dev *mdev,
 	}

 	clk_put(pipe->pxlclk);
-	clk_put(pipe->aclk);

 	of_node_put(pipe->of_output_dev);
 	of_node_put(pipe->of_output_port);
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index 0c3f101e0dce..090a5d92d5f1 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -388,8 +388,6 @@ struct komeda_pipeline {
 	struct komeda_dev *mdev;
 	/** @pxlclk: pixel clock */
 	struct clk *pxlclk;
-	/** @aclk: AXI clock */
-	struct clk *aclk;
 	/** @id: pipeline id */
 	int id;
 	/** @avail_comps: available components mask of pipeline */
--
2.17.1

[PATCH 2/3] drm/komeda: Rename main engine clk name "mclk" to "aclk"

[james qian wang (Arm Technology China)]

To avoid confusion, unify the driver main engine clk name "mclk" to
the spec name "aclk".

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
---
 .../arm/display/komeda/d71/d71_component.c    | 10 +++---
 .../gpu/drm/arm/display/komeda/komeda_crtc.c  | 34 +++++++++----------
 .../gpu/drm/arm/display/komeda/komeda_dev.c   | 18 +++++-----
 .../gpu/drm/arm/display/komeda/komeda_dev.h   |  4 +--
 .../gpu/drm/arm/display/komeda/komeda_kms.h   |  6 ++--
 .../drm/arm/display/komeda/komeda_pipeline.h  |  4 +--
 .../display/komeda/komeda_pipeline_state.c    |  4 +--
 7 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
index 769f5a2da030..87248babca1f 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -902,7 +902,7 @@ static int d71_merger_init(struct d71_dev *d71,

 static int d71_downscaling_clk_check(struct komeda_pipeline *pipe,
 				     struct drm_display_mode *mode,
-				     unsigned long mclk_rate,
+				     unsigned long aclk_rate,
 				     struct komeda_data_flow_cfg *dflow)
 {
 	u32 h_in = dflow->in_w;
@@ -912,20 +912,20 @@ static int d71_downscaling_clk_check(struct komeda_pipeline *pipe,

 	/* D71 downscaling must satisfy the following equation
 	 *
-	 *   MCLK                   h_in * v_in
+	 *   ACLK                   h_in * v_in
 	 * ------- >= ---------------------------------------------
 	 *  PXLCLK     (h_total - (1 + 2 * v_in / v_out)) * v_out
 	 *
 	 * In only horizontal downscaling situation, the right side should be
 	 * multiplied by (h_total - 3) / (h_active - 3), then equation becomes
 	 *
-	 *   MCLK          h_in
+	 *   ACLK          h_in
 	 * ------- >= ----------------
 	 *  PXLCLK     (h_active - 3)
 	 *
 	 * To avoid precision lost the equation 1 will be convert to:
 	 *
-	 *   MCLK             h_in * v_in
+	 *   ACLK             h_in * v_in
 	 * ------- >= -----------------------------------
 	 *  PXLCLK     (h_total -1 ) * v_out -  2 * v_in
 	 */
@@ -937,7 +937,7 @@ static int d71_downscaling_clk_check(struct komeda_pipeline *pipe,
 		denominator = (mode->htotal - 1) * v_out -  2 * v_in;
 	}

-	return mclk_rate * denominator >= mode->clock * 1000 * fraction ?
+	return aclk_rate * denominator >= mode->clock * 1000 * fraction ?
 	       0 : -EINVAL;
 }

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 3933f4377cc1..66c5e0d2925c 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -20,7 +20,7 @@

 static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st)
 {
-	u64 pxlclk, mclk;
+	u64 pxlclk, aclk;

 	if (!kcrtc_st->base.active) {
 		kcrtc_st->clock_ratio = 0;
@@ -28,10 +28,10 @@ static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st)
 	}

 	pxlclk = kcrtc_st->base.adjusted_mode.clock * 1000;
-	mclk = komeda_calc_mclk(kcrtc_st) << 32;
+	aclk = komeda_calc_aclk(kcrtc_st) << 32;

-	do_div(mclk, pxlclk);
-	kcrtc_st->clock_ratio = mclk;
+	do_div(aclk, pxlclk);
+	kcrtc_st->clock_ratio = aclk;
 }

 /**
@@ -75,12 +75,12 @@ komeda_crtc_atomic_check(struct drm_crtc *crtc,
 	return 0;
 }

-unsigned long komeda_calc_mclk(struct komeda_crtc_state *kcrtc_st)
+unsigned long komeda_calc_aclk(struct komeda_crtc_state *kcrtc_st)
 {
 	struct komeda_dev *mdev = kcrtc_st->base.crtc->dev->dev_private;
 	unsigned long pxlclk = kcrtc_st->base.adjusted_mode.clock;

-	return clk_round_rate(mdev->mclk, pxlclk * 1000);
+	return clk_round_rate(mdev->aclk, pxlclk * 1000);
 }

 /* For active a crtc, mainly need two parts of preparation
@@ -113,18 +113,18 @@ komeda_crtc_prepare(struct komeda_crtc *kcrtc)
 	}

 	mdev->dpmode = new_mode;
-	/* Only need to enable mclk on single display mode, but no need to
-	 * enable mclk it on dual display mode, since the dual mode always
-	 * switch from single display mode, the mclk already enabled, no need
+	/* Only need to enable aclk on single display mode, but no need to
+	 * enable aclk it on dual display mode, since the dual mode always
+	 * switch from single display mode, the aclk already enabled, no need
 	 * to enable it again.
 	 */
 	if (new_mode != KOMEDA_MODE_DUAL_DISP) {
-		err = clk_set_rate(mdev->mclk, komeda_calc_mclk(kcrtc_st));
+		err = clk_set_rate(mdev->aclk, komeda_calc_aclk(kcrtc_st));
 		if (err)
-			DRM_ERROR("failed to set mclk.\n");
-		err = clk_prepare_enable(mdev->mclk);
+			DRM_ERROR("failed to set aclk.\n");
+		err = clk_prepare_enable(mdev->aclk);
 		if (err)
-			DRM_ERROR("failed to enable mclk.\n");
+			DRM_ERROR("failed to enable aclk.\n");
 	}

 	err = clk_set_rate(master->pxlclk, pxlclk_rate);
@@ -168,7 +168,7 @@ komeda_crtc_unprepare(struct komeda_crtc *kcrtc)

 	clk_disable_unprepare(master->pxlclk);
 	if (new_mode == KOMEDA_MODE_INACTIVE)
-		clk_disable_unprepare(mdev->mclk);
+		clk_disable_unprepare(mdev->aclk);

 unlock:
 	mutex_unlock(&mdev->lock);
@@ -354,7 +354,6 @@ komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
 	if (m->flags & DRM_MODE_FLAG_INTERLACE)
 		return MODE_NO_INTERLACE;

-	/* main clock/AXI clk must be faster than pxlclk*/
 	mode_clk = m->clock * 1000;
 	pxlclk = clk_round_rate(master->pxlclk, mode_clk);
 	if (pxlclk != mode_clk) {
@@ -363,8 +362,9 @@ komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
 		return MODE_NOCLOCK;
 	}

-	if (clk_round_rate(mdev->mclk, mode_clk) < pxlclk) {
-		DRM_DEBUG_ATOMIC("mclk can't satisfy the requirement of %s-clk: %ld.\n",
+	/* main engine clock must be faster than pxlclk*/
+	if (clk_round_rate(mdev->aclk, mode_clk) < pxlclk) {
+		DRM_DEBUG_ATOMIC("engine clk can't satisfy the requirement of %s-clk: %ld.\n",
 				 m->name, pxlclk);

 		return MODE_CLOCK_HIGH;
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
index f8f6edbf6f0d..405c64dce355 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
@@ -192,15 +192,15 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
 		goto err_cleanup;
 	}

-	mdev->mclk = devm_clk_get(dev, "mclk");
-	if (IS_ERR(mdev->mclk)) {
+	mdev->aclk = devm_clk_get(dev, "aclk");
+	if (IS_ERR(mdev->aclk)) {
 		DRM_ERROR("Get engine clk failed.\n");
-		err = PTR_ERR(mdev->mclk);
-		mdev->mclk = NULL;
+		err = PTR_ERR(mdev->aclk);
+		mdev->aclk = NULL;
 		goto err_cleanup;
 	}

-	clk_prepare_enable(mdev->mclk);
+	clk_prepare_enable(mdev->aclk);

 	mdev->funcs = product->identify(mdev->reg_base, &mdev->chip);
 	if (!komeda_product_match(mdev, product->product_id)) {
@@ -300,10 +300,10 @@ void komeda_dev_destroy(struct komeda_dev *mdev)
 		mdev->reg_base = NULL;
 	}

-	if (mdev->mclk) {
-		clk_disable_unprepare(mdev->mclk);
-		devm_clk_put(dev, mdev->mclk);
-		mdev->mclk = NULL;
+	if (mdev->aclk) {
+		clk_disable_unprepare(mdev->aclk);
+		devm_clk_put(dev, mdev->aclk);
+		mdev->aclk = NULL;
 	}

 	devm_kfree(dev, mdev);
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
index 5feaed2dc93f..d1c86b6174c8 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
@@ -160,8 +160,8 @@ struct komeda_dev {
 	struct komeda_chip_info chip;
 	/** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
 	struct komeda_format_caps_table fmt_tbl;
-	/** @mclk: HW main engine clk */
-	struct clk *mclk;
+	/** @aclk: HW main engine clk */
+	struct clk *aclk;

 	/** @irq: irq number */
 	int irq;
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
index e7fa00e079a7..219fa3f0c336 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
@@ -95,7 +95,7 @@ struct komeda_crtc {
 	/** @disable_done: this flip_done is for tracing the disable */
 	struct completion *disable_done;

-	/** @clock_ratio_property: property for ratio of (mclk << 32)/pxlclk */
+	/** @clock_ratio_property: property for ratio of (aclk << 32)/pxlclk */
 	struct drm_property *clock_ratio_property;

 	/** @slave_planes_property: property for slaves of the planes */
@@ -123,7 +123,7 @@ struct komeda_crtc_state {
 	 */
 	u32 active_pipes;

-	/** @clock_ratio: ratio of (mclk << 32)/pxlclk */
+	/** @clock_ratio: ratio of (aclk << 32)/pxlclk */
 	u64 clock_ratio;

 	/** @max_slave_zorder: the maximum of slave zorder */
@@ -182,7 +182,7 @@ static inline bool has_flip_h(u32 rot)
 		return !!(rotation & DRM_MODE_REFLECT_X);
 }

-unsigned long komeda_calc_mclk(struct komeda_crtc_state *kcrtc_st);
+unsigned long komeda_calc_aclk(struct komeda_crtc_state *kcrtc_st);

 int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev);

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index 090a5d92d5f1..7af3e266bdff 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -364,12 +364,12 @@ struct komeda_data_flow_cfg {
 };

 struct komeda_pipeline_funcs {
-	/* check if the mclk (main engine clock) can satisfy the clock
+	/* check if the aclk (main engine clock) can satisfy the clock
 	 * requirements of the downscaling that specified by dflow
 	 */
 	int (*downscaling_clk_check)(struct komeda_pipeline *pipe,
 				     struct drm_display_mode *mode,
-				     unsigned long mclk_rate,
+				     unsigned long aclk_rate,
 				     struct komeda_data_flow_cfg *dflow);
 	/* dump_register: Optional, dump registers to seq_file */
 	void (*dump_register)(struct komeda_pipeline *pipe,
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 44a51d84e602..257f0aedd11d 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -473,9 +473,9 @@ komeda_scaler_check_cfg(struct komeda_scaler *scaler,

 		err = pipe->funcs->downscaling_clk_check(pipe,
 					&kcrtc_st->base.adjusted_mode,
-					komeda_calc_mclk(kcrtc_st), dflow);
+					komeda_calc_aclk(kcrtc_st), dflow);
 		if (err) {
-			DRM_DEBUG_ATOMIC("mclk can't satisfy the clock requirement of the downscaling\n");
+			DRM_DEBUG_ATOMIC("aclk can't satisfy the clock requirement of the downscaling\n");
 			return err;
 		}
 	}
--
2.17.1

[PATCH 3/3] dt/bindings: drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK

[james qian wang (Arm Technology China)]

Current komeda driver uses three dedicated clks for a specific purpose:
- mclk: main engine clock
- pclk: APB clock
- pipeline->aclk: AXI clock.

But per spec the komeda HW only has three input clks:
- ACLK: used for AXI masters, APB slave and most pipeline processing
- PXCLK for pipeline 0: output pixel clock for pipeline 0
- PXCLK for pipeline 1: output pixel clock for pipeline 1

So one ACLK is enough, no need to split it to three mclk/pclk/axiclk.

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
---
 .../devicetree/bindings/display/arm,komeda.txt   | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm,komeda.txt
index b12c0453a421..8513695ee47f 100644
--- a/Documentation/devicetree/bindings/display/arm,komeda.txt
+++ b/Documentation/devicetree/bindings/display/arm,komeda.txt
@@ -7,8 +7,7 @@ Required properties:
 - clocks: A list of phandle + clock-specifier pairs, one for each entry
     in 'clock-names'
 - clock-names: A list of clock names. It should contain:
-      - "mclk": for the main processor clock
-      - "pclk": for the APB interface clock
+      - "aclk": for the main processor clock
 - #address-cells: Must be 1
 - #size-cells: Must be 0
 - iommus: configure the stream id to IOMMU, Must be configured if want to
@@ -24,7 +23,6 @@ pipeline node should provide properties:
     in 'clock-names'
 - clock-names: should contain:
       - "pxclk": pixel clock
-      - "aclk": AXI interface clock

 - port: each pipeline connect to an encoder input port. The connection is
     modeled using the OF graph bindings specified in
@@ -46,15 +44,15 @@ Example:
 		compatible = "arm,mali-d71";
 		reg = <0xc00000 0x20000>;
 		interrupts = <0 168 4>;
-		clocks = <&dpu_mclk>, <&dpu_aclk>;
-		clock-names = "mclk", "pclk";
+		clocks = <&dpu_aclk>;
+		clock-names = "aclk";
 		iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
 			<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
 			<&smmu 8>, <&smmu 9>;

 		dp0_pipe0: pipeline@0 {
-			clocks = <&fpgaosc2>, <&dpu_aclk>;
-			clock-names = "pxclk", "aclk";
+			clocks = <&fpgaosc2>;
+			clock-names = "pxclk";
 			reg = <0>;

 			port {
@@ -65,8 +63,8 @@ Example:
 		};

 		dp0_pipe1: pipeline@1 {
-			clocks = <&fpgaosc2>, <&dpu_aclk>;
-			clock-names = "pxclk", "aclk";
+			clocks = <&fpgaosc2>;
+			clock-names = "pxclk";
 			reg = <1>;

 			port {
--
2.17.1