[tip:WIP.x86/cpu 11/17] arch/x86/entry/entry_64.S:1214: Error: no such instruction: `save_and_set_gsbase scratch_reg=%rax save_reg=%rbx'

[tip:WIP.x86/cpu 11/17] arch/x86/entry/entry_64.S:1214: Error: no such instruction: `save_and_set_gsbase scratch_reg=%rax save_reg=%rbx'

[kbuild test robot]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.x86/cpu
head:   707e6befd43ba8d754485d8d02ed4f49ec8ec667
commit: 54f792cc63c56d994651c8e83d059d6fac00fbf9 [11/17] x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit
config: x86_64-kexec (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        git checkout 54f792cc63c56d994651c8e83d059d6fac00fbf9
        # save the attached .config to linux build tree
        make ARCH=x86_64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   arch/x86/entry/entry_64.S: Assembler messages:
>> arch/x86/entry/entry_64.S:1214: Error: no such instruction: `save_and_set_gsbase scratch_reg=%rax save_reg=%rbx'

vim +1214 arch/x86/entry/entry_64.S

  1165	
  1166	/*
  1167	 * Save all registers in pt_regs. Return GSBASE related information
  1168	 * in EBX depending on the availability of the FSGSBASE instructions:
  1169	 *
  1170	 * FSGSBASE	R/EBX
  1171	 *     N        0 -> SWAPGS on exit
  1172	 *              1 -> no SWAPGS on exit
  1173	 *
  1174	 *     Y        GSBASE value at entry, must be restored in paranoid_exit
  1175	 */
  1176	ENTRY(paranoid_entry)
  1177		UNWIND_HINT_FUNC
  1178		cld
  1179		PUSH_AND_CLEAR_REGS save_ret=1
  1180		ENCODE_FRAME_POINTER 8
  1181	
  1182		/*
  1183		 * Always stash CR3 in %r14.  This value will be restored,
  1184		 * verbatim, at exit.  Needed if paranoid_entry interrupted
  1185		 * another entry that already switched to the user CR3 value
  1186		 * but has not yet returned to userspace.
  1187		 *
  1188		 * This is also why CS (stashed in the "iret frame" by the
  1189		 * hardware at entry) can not be used: this may be a return
  1190		 * to kernel code, but with a user CR3 value.
  1191		 *
  1192		 * Switching CR3 does not depend on kernel GSBASE so it can
  1193		 * be done before switching to the kernel GSBASE. This is
  1194		 * required for FSGSBASE because the kernel GSBASE has to
  1195		 * be retrieved from a kernel internal table.
  1196		 */
  1197		SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
  1198	
  1199	        /*
  1200		 * Handling GSBASE depends on the availability of FSGSBASE.
  1201		 *
  1202		 * Without FSGSBASE the kernel enforces that negative GSBASE
  1203		 * values indicate kernel GSBASE. With FSGSBASE no assumptions
  1204		 * can be made about the GSBASE value when entering from user
  1205		 * space.
  1206		*/
  1207		ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
  1208	
  1209		/*
  1210		 * Read the current GSBASE and store it in in %rbx unconditionally,
  1211		 * retrieve and set the current CPUs kernel GSBASE. The stored value
  1212		 * has to be restored in paranoid_exit unconditionally.
  1213		 */
> 1214		SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
  1215		ret
  1216	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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