[PATCH 1/2] clk: imx8mm: Fix typo of pwm3 clock's mux option #4

[PATCH 1/2] clk: imx8mm: Fix typo of pwm3 clock's mux option #4

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4
should be sys_pll3_out, sys3_pll2_out is a typo, fix it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 56d53dd..516e68d 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -287,7 +287,7 @@ static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
 					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
 
 static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
-					 "sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
 
 static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
 					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
-- 
2.7.4

[PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 516e68d..d1a84f7 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
 					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
 
 static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
-					 "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };
+					 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
 
 static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
 					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
-- 
2.7.4

RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Jacky Bai]

OK for me.

BR
Jacky Bai
> -----Original Message-----
> From: Anson.Huang@nxp.com [mailto:Anson.Huang@nxp.com]
> Sent: Tuesday, June 25, 2019 3:06 PM
> To: mturquette@baylibre.com; sboyd@kernel.org; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> Leonard Crestez <leonard.crestez@nxp.com>; Jacky Bai <ping.bai@nxp.com>;
> Peng Fan <peng.fan@nxp.com>; linux-clk@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: dl-linux-imx <linux-imx@nxp.com>
> Subject: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be
> sys_pll1_80m
> 
> From: Anson Huang <Anson.Huang@nxp.com>
> 
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> sys_pll1_800m, correct it.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
>  drivers/clk/imx/clk-imx8mm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 516e68d..d1a84f7 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] =
> {"osc_24m", "sys_pll2_100m", "sys_pll1_1
>  					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m",
> "video_pll1_out", };
> 
>  static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m",
> "sys_pll1_400m", "sys_pll1_40m",
> -					 "video_pll1_out", "sys_pll1_800m",
> "audio_pll1_out", "clk_ext1" };
> +					 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out",
> "clk_ext1" };
> 
>  static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m",
> "sys_pll1_160m", "vpu_pll_out",
>  					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m",
> "sys_pll2_166m", };
> --
> 2.7.4

Re: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Stephen Boyd]

Quoting Anson.Huang@nxp.com (2019-06-25 00:06:02)
> From: Anson Huang <Anson.Huang@nxp.com>
> 
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
> NOT sys_pll1_800m, correct it.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Any Fixes tags?

RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Anson Huang]

Hi, Stephen

> Quoting Anson.Huang@nxp.com (2019-06-25 00:06:02)
> > From: Anson Huang <Anson.Huang@nxp.com>
> >
> > i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> > sys_pll1_800m, correct it.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> 
> Any Fixes tags?

Oops, I forgot to add fixed tags, just resent the patch set, sorry for that.

Thanks,
Anson