* [PATCH 02/25] clocksource/drivers/ixp4xx: Implement delay timer
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 03/25] clocksource/drivers/arc_timer: Use BIT() instead of _BITUL() Daniel Lezcano
` (22 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Linus Walleij, Linus Walleij, Imre Kaloz,
Krzysztof Halasa,
moderated list:ARM/INTEL IXP4XX ARM ARCHITECTURE
From: Linus Walleij <linus.walleij@linaro.org>
This adds delay timer functionality to the IXP4xx
timer driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-ixp4xx.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/timer-ixp4xx.c b/drivers/clocksource/timer-ixp4xx.c
index 5c2190b654cd..9396745e1c17 100644
--- a/drivers/clocksource/timer-ixp4xx.c
+++ b/drivers/clocksource/timer-ixp4xx.c
@@ -75,14 +75,19 @@ to_ixp4xx_timer(struct clock_event_device *evt)
return container_of(evt, struct ixp4xx_timer, clkevt);
}
-static u64 notrace ixp4xx_read_sched_clock(void)
+static unsigned long ixp4xx_read_timer(void)
{
return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
}
+static u64 notrace ixp4xx_read_sched_clock(void)
+{
+ return ixp4xx_read_timer();
+}
+
static u64 ixp4xx_clocksource_read(struct clocksource *c)
{
- return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
+ return ixp4xx_read_timer();
}
static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
@@ -224,6 +229,13 @@ static __init int ixp4xx_timer_register(void __iomem *base,
sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
+#ifdef CONFIG_ARM
+ /* Also use this timer for delays */
+ tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
+ tmr->delay_timer.freq = timer_freq;
+ register_current_timer_delay(&tmr->delay_timer);
+#endif
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 03/25] clocksource/drivers/arc_timer: Use BIT() instead of _BITUL()
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
2019-06-26 14:46 ` [PATCH 02/25] clocksource/drivers/ixp4xx: Implement delay timer Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 04/25] clocksource/drivers/exynos_mct: Increase priority over ARM arch timer Daniel Lezcano
` (21 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Masahiro Yamada, Vineet Gupta,
open list:SYNOPSYS ARC ARCHITECTURE
From: Masahiro Yamada <yamada.masahiro@socionext.com>
This is in-kernel C code, so there is no reason to use _BITUL().
Replace it with equivalent BIT().
I added #include <linux/bits.h> explicitly although it has been included
by other headers eventually.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/arc_timer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index b28970ca4a7a..b1f21bf3b83c 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -16,6 +16,7 @@
*/
#include <linux/interrupt.h>
+#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
@@ -142,7 +143,7 @@ static u64 arc_read_rtc(struct clocksource *cs)
l = read_aux_reg(AUX_RTC_LOW);
h = read_aux_reg(AUX_RTC_HIGH);
status = read_aux_reg(AUX_RTC_CTRL);
- } while (!(status & _BITUL(31)));
+ } while (!(status & BIT(31)));
return (((u64)h) << 32) | l;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 04/25] clocksource/drivers/exynos_mct: Increase priority over ARM arch timer
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
2019-06-26 14:46 ` [PATCH 02/25] clocksource/drivers/ixp4xx: Implement delay timer Daniel Lezcano
2019-06-26 14:46 ` [PATCH 03/25] clocksource/drivers/arc_timer: Use BIT() instead of _BITUL() Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 05/25] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Daniel Lezcano
` (20 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Marek Szyprowski, Kukjin Kim, Krzysztof Kozlowski,
Will Deacon, Palmer Dabbelt, Borislav Petkov, Rafael J. Wysocki,
Lucas Stach, Kulkarni, Ganapatrao, Peter Zijlstra, Guo Ren,
Joseph Lo, Anju T Sudhakar, Hoan Tran,
moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES,
moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
From: Marek Szyprowski <m.szyprowski@samsung.com>
Exynos SoCs based on CA7/CA15 have 2 timer interfaces: custom Exynos MCT
(Multi Core Timer) and standard ARM Architected Timers.
There are use cases, where both timer interfaces are used simultanously.
One of such examples is using Exynos MCT for the main system timer and
ARM Architected Timers for the KVM and virtualized guests (KVM requires
arch timers).
Exynos Multi-Core Timer driver (exynos_mct) must be however started
before ARM Architected Timers (arch_timer), because they both share some
common hardware blocks (global system counter) and turning on MCT is
needed to get ARM Architected Timer working properly.
To ensure selecting Exynos MCT as the main system timer, increase MCT
timer rating. To ensure proper starting order of both timers during
suspend/resume cycle, increase MCT hotplug priority over ARM Archictected
Timers.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/exynos_mct.c | 4 ++--
include/linux/cpuhotplug.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 34bd250d46c6..6aa10cbc1d59 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -209,7 +209,7 @@ static void exynos4_frc_resume(struct clocksource *cs)
static struct clocksource mct_frc = {
.name = "mct-frc",
- .rating = 400,
+ .rating = 450, /* use value higher than ARM arch timer */
.read = exynos4_frc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -464,7 +464,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu)
evt->set_state_oneshot_stopped = set_state_shutdown;
evt->tick_resume = set_state_shutdown;
evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->rating = 450;
+ evt->rating = 500; /* use value higher than ARM arch timer */
exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 5c6062206760..87c211adf49e 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -116,10 +116,10 @@ enum cpuhp_state {
CPUHP_AP_PERF_ARM_ACPI_STARTING,
CPUHP_AP_PERF_ARM_STARTING,
CPUHP_AP_ARM_L2X0_STARTING,
+ CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
CPUHP_AP_ARM_ARCH_TIMER_STARTING,
CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
CPUHP_AP_JCORE_TIMER_STARTING,
- CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
CPUHP_AP_ARM_TWD_STARTING,
CPUHP_AP_QCOM_TIMER_STARTING,
CPUHP_AP_TEGRA_TIMER_STARTING,
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 05/25] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (2 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 04/25] clocksource/drivers/exynos_mct: Increase priority over ARM arch timer Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 06/25] clocksource/drivers/tegra: Unify timer code Daniel Lezcano
` (19 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Assign TMR1-4 per-CPU core on 32bit Tegra's in a way it is done for
Tegra210. In a result each core can handle its own timer events, less
code is unique to ARM64 and Tegra's clock events driver now has higher
rating on all Tegra's, replacing the ARM's TWD timer which isn't very
accurate due to the clock rate jitter caused by CPU frequency scaling.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 120 ++++++++++------------------
1 file changed, 43 insertions(+), 77 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 1e7ece279730..4b30ba6228c1 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -40,13 +40,18 @@
#define TIMER_PCR_INTR_CLR BIT(30)
#ifdef CONFIG_ARM
-#define TIMER_CPU0 0x50 /* TIMER3 */
+#define TIMER_CPU0 0x00 /* TIMER1 */
+#define TIMER_CPU2 0x50 /* TIMER3 */
+#define TIMER1_IRQ_IDX 0
+#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu)
+#define TIMER_BASE_FOR_CPU(cpu) \
+ (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2))
#else
#define TIMER_CPU0 0x90 /* TIMER10 */
#define TIMER10_IRQ_IDX 10
#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu)
-#endif
#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+#endif
static u32 usec_config;
static void __iomem *timer_reg_base;
@@ -109,7 +114,6 @@ static void tegra_timer_resume(struct clock_event_device *evt)
writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
}
-#ifdef CONFIG_ARM64
static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
@@ -150,33 +154,8 @@ static int tegra_timer_stop(unsigned int cpu)
return 0;
}
-#else /* CONFIG_ARM */
-static struct timer_of tegra_to = {
- .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
-
- .clkevt = {
- .name = "tegra_timer",
- .rating = 300,
- .features = CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_DYNIRQ,
- .set_next_event = tegra_timer_set_next_event,
- .set_state_shutdown = tegra_timer_shutdown,
- .set_state_periodic = tegra_timer_set_periodic,
- .set_state_oneshot = tegra_timer_shutdown,
- .tick_resume = tegra_timer_shutdown,
- .suspend = tegra_timer_suspend,
- .resume = tegra_timer_resume,
- .cpumask = cpu_possible_mask,
- },
-
- .of_irq = {
- .index = 2,
- .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
- .handler = tegra_timer_isr,
- },
-};
+#ifdef CONFIG_ARM
static u64 notrace tegra_read_sched_clock(void)
{
return readl(timer_reg_base + TIMERUS_CNTR_1US);
@@ -213,10 +192,12 @@ static struct clocksource suspend_rtc_clocksource = {
};
#endif
-static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
+static int tegra_init_timer(struct device_node *np, bool tegra20)
{
- int ret = 0;
+ struct timer_of *to;
+ int cpu, ret;
+ to = this_cpu_ptr(&tegra_to);
ret = timer_of_init(np, to);
if (ret < 0)
goto out;
@@ -258,29 +239,19 @@ static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
goto out;
}
- writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
-
-out:
- return ret;
-}
-
-#ifdef CONFIG_ARM64
-static int __init tegra_init_timer(struct device_node *np)
-{
- int cpu, ret = 0;
- struct timer_of *to;
-
- to = this_cpu_ptr(&tegra_to);
- ret = tegra_timer_common_init(np, to);
- if (ret < 0)
- goto out;
+ writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
for_each_possible_cpu(cpu) {
- struct timer_of *cpu_to;
+ struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
+
+ /*
+ * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
+ * parent clock.
+ */
+ if (tegra20)
+ cpu_to->of_clk.rate = 1000000;
- cpu_to = per_cpu_ptr(&tegra_to, cpu);
cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
- cpu_to->of_clk.rate = timer_of_rate(to);
cpu_to->clkevt.cpumask = cpumask_of(cpu);
cpu_to->clkevt.irq =
irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
@@ -322,43 +293,39 @@ static int __init tegra_init_timer(struct device_node *np)
timer_of_cleanup(to);
return ret;
}
+
+#ifdef CONFIG_ARM64
+static int __init tegra210_init_timer(struct device_node *np)
+{
+ return tegra_init_timer(np, false);
+}
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
#else /* CONFIG_ARM */
-static int __init tegra_init_timer(struct device_node *np)
+static int __init tegra20_init_timer(struct device_node *np)
{
- int ret = 0;
+ struct timer_of *to;
+ int err;
- ret = tegra_timer_common_init(np, &tegra_to);
- if (ret < 0)
- goto out;
+ err = tegra_init_timer(np, true);
+ if (err)
+ return err;
- tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
- tegra_to.of_clk.rate = 1000000; /* microsecond timer */
+ to = this_cpu_ptr(&tegra_to);
sched_clock_register(tegra_read_sched_clock, 32,
- timer_of_rate(&tegra_to));
- ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
- "timer_us", timer_of_rate(&tegra_to),
+ timer_of_rate(to));
+ err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
+ "timer_us", timer_of_rate(to),
300, 32, clocksource_mmio_readl_up);
- if (ret) {
- pr_err("Failed to register clocksource\n");
- goto out;
- }
+ if (err)
+ pr_err("Failed to register clocksource: %d\n", err);
tegra_delay_timer.read_current_timer =
tegra_delay_timer_read_counter_long;
- tegra_delay_timer.freq = timer_of_rate(&tegra_to);
+ tegra_delay_timer.freq = timer_of_rate(to);
register_current_timer_delay(&tegra_delay_timer);
- clockevents_config_and_register(&tegra_to.clkevt,
- timer_of_rate(&tegra_to),
- 0x1,
- 0x1fffffff);
-
- return ret;
-out:
- timer_of_cleanup(&tegra_to);
-
- return ret;
+ return 0;
}
static int __init tegra20_init_rtc(struct device_node *np)
@@ -374,6 +341,5 @@ static int __init tegra20_init_rtc(struct device_node *np)
return 0;
}
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
#endif
-TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 06/25] clocksource/drivers/tegra: Unify timer code
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (3 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 05/25] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 07/25] clocksource/drivers/tegra: Reset hardware state on init Daniel Lezcano
` (18 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Tegra132 is 64bit platform and it has the tegra20-timer hardware unit.
Right now the corresponding timer code isn't compiled for ARM64, remove
ifdef'iness from the code and compile tegra20-timer for both 32 and 64 bit
platforms. Also note that like the older generations, Tegra210 has the
microseconds counter, hence the timer_us clocksource is now made available
for Tegra210 as well.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 111 +++++++++++++++-------------
1 file changed, 60 insertions(+), 51 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 4b30ba6228c1..acd68c77fa91 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -21,10 +21,6 @@
#include "timer-of.h"
-#ifdef CONFIG_ARM
-#include <asm/mach/time.h>
-#endif
-
#define RTC_SECONDS 0x08
#define RTC_SHADOW_SECONDS 0x0c
#define RTC_MILLISECONDS 0x10
@@ -39,25 +35,17 @@
#define TIMER_PCR 0x4
#define TIMER_PCR_INTR_CLR BIT(30)
-#ifdef CONFIG_ARM
-#define TIMER_CPU0 0x00 /* TIMER1 */
-#define TIMER_CPU2 0x50 /* TIMER3 */
+#define TIMER1_BASE 0x00
+#define TIMER2_BASE 0x08
+#define TIMER3_BASE 0x50
+#define TIMER4_BASE 0x58
+#define TIMER10_BASE 0x90
+
#define TIMER1_IRQ_IDX 0
-#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu)
-#define TIMER_BASE_FOR_CPU(cpu) \
- (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2))
-#else
-#define TIMER_CPU0 0x90 /* TIMER10 */
#define TIMER10_IRQ_IDX 10
-#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu)
-#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
-#endif
static u32 usec_config;
static void __iomem *timer_reg_base;
-#ifdef CONFIG_ARM
-static struct delay_timer tegra_delay_timer;
-#endif
static int tegra_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
@@ -155,17 +143,23 @@ static int tegra_timer_stop(unsigned int cpu)
return 0;
}
-#ifdef CONFIG_ARM
static u64 notrace tegra_read_sched_clock(void)
{
return readl(timer_reg_base + TIMERUS_CNTR_1US);
}
+#ifdef CONFIG_ARM
static unsigned long tegra_delay_timer_read_counter_long(void)
{
return readl(timer_reg_base + TIMERUS_CNTR_1US);
}
+static struct delay_timer tegra_delay_timer = {
+ .read_current_timer = tegra_delay_timer_read_counter_long,
+ .freq = 1000000,
+};
+#endif
+
static struct timer_of suspend_rtc_to = {
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
};
@@ -190,9 +184,34 @@ static struct clocksource suspend_rtc_clocksource = {
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
};
-#endif
-static int tegra_init_timer(struct device_node *np, bool tegra20)
+static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
+{
+ if (tegra20) {
+ switch (cpu) {
+ case 0:
+ return TIMER1_BASE;
+ case 1:
+ return TIMER2_BASE;
+ case 2:
+ return TIMER3_BASE;
+ default:
+ return TIMER4_BASE;
+ }
+ }
+
+ return TIMER10_BASE + cpu * 8;
+}
+
+static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
+{
+ if (tegra20)
+ return TIMER1_IRQ_IDX + cpu;
+
+ return TIMER10_IRQ_IDX + cpu;
+}
+
+static int __init tegra_init_timer(struct device_node *np, bool tegra20)
{
struct timer_of *to;
int cpu, ret;
@@ -243,6 +262,8 @@ static int tegra_init_timer(struct device_node *np, bool tegra20)
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ unsigned int base = tegra_base_for_cpu(cpu, tegra20);
+ unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
/*
* TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
@@ -251,10 +272,10 @@ static int tegra_init_timer(struct device_node *np, bool tegra20)
if (tegra20)
cpu_to->of_clk.rate = 1000000;
- cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+ cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ cpu_to->of_base.base = timer_reg_base + base;
cpu_to->clkevt.cpumask = cpumask_of(cpu);
- cpu_to->clkevt.irq =
- irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+ cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
if (!cpu_to->clkevt.irq) {
pr_err("%s: can't map IRQ for CPU%d\n",
__func__, cpu);
@@ -274,6 +295,18 @@ static int tegra_init_timer(struct device_node *np, bool tegra20)
}
}
+ sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+
+ ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
+ "timer_us", 1000000,
+ 300, 32, clocksource_mmio_readl_up);
+ if (ret)
+ pr_err("failed to register clocksource: %d\n", ret);
+
+#ifdef CONFIG_ARM
+ register_current_timer_delay(&tegra_delay_timer);
+#endif
+
cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
tegra_timer_stop);
@@ -294,39 +327,17 @@ static int tegra_init_timer(struct device_node *np, bool tegra20)
return ret;
}
-#ifdef CONFIG_ARM64
static int __init tegra210_init_timer(struct device_node *np)
{
return tegra_init_timer(np, false);
}
TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
-#else /* CONFIG_ARM */
+
static int __init tegra20_init_timer(struct device_node *np)
{
- struct timer_of *to;
- int err;
-
- err = tegra_init_timer(np, true);
- if (err)
- return err;
-
- to = this_cpu_ptr(&tegra_to);
-
- sched_clock_register(tegra_read_sched_clock, 32,
- timer_of_rate(to));
- err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
- "timer_us", timer_of_rate(to),
- 300, 32, clocksource_mmio_readl_up);
- if (err)
- pr_err("Failed to register clocksource: %d\n", err);
-
- tegra_delay_timer.read_current_timer =
- tegra_delay_timer_read_counter_long;
- tegra_delay_timer.freq = timer_of_rate(to);
- register_current_timer_delay(&tegra_delay_timer);
-
- return 0;
+ return tegra_init_timer(np, true);
}
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
static int __init tegra20_init_rtc(struct device_node *np)
{
@@ -341,5 +352,3 @@ static int __init tegra20_init_rtc(struct device_node *np)
return 0;
}
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
-#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 07/25] clocksource/drivers/tegra: Reset hardware state on init
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (4 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 06/25] clocksource/drivers/tegra: Unify timer code Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 08/25] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Daniel Lezcano
` (17 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Reset timer's hardware state to ensure that initially it is in a
predictable state.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index acd68c77fa91..3e4f12aee8df 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -123,6 +123,9 @@ static int tegra_timer_setup(unsigned int cpu)
{
struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+ writel(0, timer_of_base(to) + TIMER_PTV);
+ writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
+
irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
enable_irq(to->clkevt.irq);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 08/25] clocksource/drivers/tegra: Replace readl/writel with relaxed versions
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (5 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 07/25] clocksource/drivers/tegra: Reset hardware state on init Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 09/25] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Daniel Lezcano
` (16 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
The readl/writel functions are inserting memory barrier to ensure that
outstanding memory writes are completed, this results in L2 cache syncing
being done on Tegra20 and Tegra30 which isn't a very cheap operation.
Replace all readl/writel occurrences in the code with the relaxed versions
since there is no need for the memory-access syncing.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 35 +++++++++++++++--------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 3e4f12aee8df..276b55f6ada0 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -52,9 +52,9 @@ static int tegra_timer_set_next_event(unsigned long cycles,
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PTV_EN |
- ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
- reg_base + TIMER_PTV);
+ writel_relaxed(TIMER_PTV_EN |
+ ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+ reg_base + TIMER_PTV);
return 0;
}
@@ -63,7 +63,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(0, reg_base + TIMER_PTV);
+ writel_relaxed(0, reg_base + TIMER_PTV);
return 0;
}
@@ -72,9 +72,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PTV_EN | TIMER_PTV_PER |
- ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
- reg_base + TIMER_PTV);
+ writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
+ ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+ reg_base + TIMER_PTV);
return 0;
}
@@ -84,7 +84,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
evt->event_handler(evt);
return IRQ_HANDLED;
@@ -94,12 +94,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
}
static void tegra_timer_resume(struct clock_event_device *evt)
{
- writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+ writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
}
static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
@@ -123,8 +123,8 @@ static int tegra_timer_setup(unsigned int cpu)
{
struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
- writel(0, timer_of_base(to) + TIMER_PTV);
- writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
+ writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
+ writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
enable_irq(to->clkevt.irq);
@@ -148,13 +148,13 @@ static int tegra_timer_stop(unsigned int cpu)
static u64 notrace tegra_read_sched_clock(void)
{
- return readl(timer_reg_base + TIMERUS_CNTR_1US);
+ return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
}
#ifdef CONFIG_ARM
static unsigned long tegra_delay_timer_read_counter_long(void)
{
- return readl(timer_reg_base + TIMERUS_CNTR_1US);
+ return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
}
static struct delay_timer tegra_delay_timer = {
@@ -175,8 +175,9 @@ static struct timer_of suspend_rtc_to = {
*/
static u64 tegra_rtc_read_ms(struct clocksource *cs)
{
- u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
- u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
+ void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
+ u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
+ u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
return (u64)s * MSEC_PER_SEC + ms;
}
@@ -261,7 +262,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
goto out;
}
- writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+ writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 09/25] clocksource/drivers/tegra: Release all IRQ's on request_irq() error
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (6 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 08/25] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 10/25] clocksource/drivers/tegra: Minor code clean up Daniel Lezcano
` (15 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Release all requested IRQ's on the request error to properly clean up
allocated resources.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 276b55f6ada0..e2ef6b8211a5 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -284,7 +284,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
pr_err("%s: can't map IRQ for CPU%d\n",
__func__, cpu);
ret = -EINVAL;
- goto out;
+ goto out_irq;
}
irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
@@ -294,7 +294,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
if (ret) {
pr_err("%s: cannot setup irq %d for CPU%d\n",
__func__, cpu_to->clkevt.irq, cpu);
- ret = -EINVAL;
+ irq_dispose_mapping(cpu_to->clkevt.irq);
+ cpu_to->clkevt.irq = 0;
goto out_irq;
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 10/25] clocksource/drivers/tegra: Minor code clean up
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (7 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 09/25] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 11/25] clocksource/drivers/tegra: Support COMPILE_TEST universally Daniel Lezcano
` (14 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Correct typo and use proper upper casing for acronyms in the comments,
use common style for error messages, prepend error messages with
"tegra-timer:", add error message for cpuhp_setup_state() failure and
clean up whitespaces in the code to fix checkpatch warnings.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++-------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index e2ef6b8211a5..6a3704142f31 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -6,6 +6,8 @@
* Colin Cross <ccross@google.com>
*/
+#define pr_fmt(fmt) "tegra-timer: " fmt
+
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
@@ -21,13 +23,13 @@
#include "timer-of.h"
-#define RTC_SECONDS 0x08
-#define RTC_SHADOW_SECONDS 0x0c
-#define RTC_MILLISECONDS 0x10
+#define RTC_SECONDS 0x08
+#define RTC_SHADOW_SECONDS 0x0c
+#define RTC_MILLISECONDS 0x10
-#define TIMERUS_CNTR_1US 0x10
-#define TIMERUS_USEC_CFG 0x14
-#define TIMERUS_CNTR_FREEZE 0x4c
+#define TIMERUS_CNTR_1US 0x10
+#define TIMERUS_USEC_CFG 0x14
+#define TIMERUS_CNTR_FREEZE 0x4c
#define TIMER_PTV 0x0
#define TIMER_PTV_EN BIT(31)
@@ -48,7 +50,7 @@ static u32 usec_config;
static void __iomem *timer_reg_base;
static int tegra_timer_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
+ struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
@@ -169,15 +171,17 @@ static struct timer_of suspend_rtc_to = {
/*
* tegra_rtc_read - Reads the Tegra RTC registers
- * Care must be taken that this funciton is not called while the
+ * Care must be taken that this function is not called while the
* tegra_rtc driver could be executing to avoid race conditions
* on the RTC shadow register
*/
static u64 tegra_rtc_read_ms(struct clocksource *cs)
{
void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
+
u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
+
return (u64)s * MSEC_PER_SEC + ms;
}
@@ -222,7 +226,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
to = this_cpu_ptr(&tegra_to);
ret = timer_of_init(np, to);
- if (ret < 0)
+ if (ret)
goto out;
timer_reg_base = timer_of_base(to);
@@ -281,8 +285,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
cpu_to->clkevt.cpumask = cpumask_of(cpu);
cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
if (!cpu_to->clkevt.irq) {
- pr_err("%s: can't map IRQ for CPU%d\n",
- __func__, cpu);
+ pr_err("failed to map irq for cpu%d\n", cpu);
ret = -EINVAL;
goto out_irq;
}
@@ -292,8 +295,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
IRQF_TIMER | IRQF_NOBALANCING,
cpu_to->clkevt.name, &cpu_to->clkevt);
if (ret) {
- pr_err("%s: cannot setup irq %d for CPU%d\n",
- __func__, cpu_to->clkevt.irq, cpu);
+ pr_err("failed to set up irq for cpu%d: %d\n",
+ cpu, ret);
irq_dispose_mapping(cpu_to->clkevt.irq);
cpu_to->clkevt.irq = 0;
goto out_irq;
@@ -312,11 +315,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
register_current_timer_delay(&tegra_delay_timer);
#endif
- cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
- "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
- tegra_timer_stop);
+ ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+ "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+ tegra_timer_stop);
+ if (ret)
+ pr_err("failed to set up cpu hp state: %d\n", ret);
return ret;
+
out_irq:
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to;
@@ -329,6 +335,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
}
out:
timer_of_cleanup(to);
+
return ret;
}
@@ -352,8 +359,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
if (ret)
return ret;
- clocksource_register_hz(&suspend_rtc_clocksource, 1000);
-
- return 0;
+ return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
}
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 11/25] clocksource/drivers/tegra: Support COMPILE_TEST universally
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (8 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 10/25] clocksource/drivers/tegra: Minor code clean up Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 12/25] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's Daniel Lezcano
` (13 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx; +Cc: linux-kernel, Dmitry Osipenko
From: Dmitry Osipenko <digetx@gmail.com>
Remove build dependency on ARM for compile-testing to allow non-arch
specific build-bots (like Intel's test robot) to compile the driver and
report about problems.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3300739edce4..d17a347e813a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -140,7 +140,7 @@ config TEGRA_TIMER
bool "Tegra timer driver" if COMPILE_TEST
select CLKSRC_MMIO
select TIMER_OF
- depends on ARM || ARM64
+ depends on ARCH_TEGRA || COMPILE_TEST
help
Enables support for the Tegra driver.
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 12/25] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (9 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 11/25] clocksource/drivers/tegra: Support COMPILE_TEST universally Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 13/25] clocksource/drivers/tegra: Rename timer-tegra20.c to timer-tegra.c Daniel Lezcano
` (12 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Arch-timer is more preferable for a range of Tegra SoC generations as
it has higher precision and is not affect by any kind of problems.
Pointed-out-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra20.c | 30 +++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 6a3704142f31..ed1454000ea9 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -109,7 +109,6 @@ static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
.clkevt = {
.name = "tegra_timer",
- .rating = 460,
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = tegra_timer_set_next_event,
.set_state_shutdown = tegra_timer_shutdown,
@@ -219,7 +218,8 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
return TIMER10_IRQ_IDX + cpu;
}
-static int __init tegra_init_timer(struct device_node *np, bool tegra20)
+static int __init tegra_init_timer(struct device_node *np, bool tegra20,
+ int rating)
{
struct timer_of *to;
int cpu, ret;
@@ -282,6 +282,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
cpu_to = per_cpu_ptr(&tegra_to, cpu);
cpu_to->of_base.base = timer_reg_base + base;
+ cpu_to->clkevt.rating = rating;
cpu_to->clkevt.cpumask = cpumask_of(cpu);
cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
if (!cpu_to->clkevt.irq) {
@@ -341,13 +342,34 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20)
static int __init tegra210_init_timer(struct device_node *np)
{
- return tegra_init_timer(np, false);
+ /*
+ * Arch-timer can't survive across power cycle of CPU core and
+ * after CPUPORESET signal due to a system design shortcoming,
+ * hence tegra-timer is more preferable on Tegra210.
+ */
+ return tegra_init_timer(np, false, 460);
}
TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
static int __init tegra20_init_timer(struct device_node *np)
{
- return tegra_init_timer(np, true);
+ int rating;
+
+ /*
+ * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
+ * that timer runs off the CPU clock and hence is subjected to
+ * a jitter caused by DVFS clock rate changes. Tegra-timer is
+ * more preferable for older Tegra's, while later SoC generations
+ * have arch-timer as a main per-CPU timer and it is not affected
+ * by DVFS changes.
+ */
+ if (of_machine_is_compatible("nvidia,tegra20") ||
+ of_machine_is_compatible("nvidia,tegra30"))
+ rating = 460;
+ else
+ rating = 330;
+
+ return tegra_init_timer(np, true, rating);
}
TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 13/25] clocksource/drivers/tegra: Rename timer-tegra20.c to timer-tegra.c
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (10 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 12/25] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 14/25] clocksource/drivers/sysctr: Add nxp system counter timer driver support Daniel Lezcano
` (11 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx; +Cc: linux-kernel, Dmitry Osipenko
From: Dmitry Osipenko <digetx@gmail.com>
Rename driver's source file to better reflect that it's not specific to
older SoC generations.
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Makefile | 2 +-
drivers/clocksource/{timer-tegra20.c => timer-tegra.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/clocksource/{timer-tegra20.c => timer-tegra.c} (100%)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 236858fa7fbf..4145b21eaed3 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -36,7 +36,7 @@ obj-$(CONFIG_U300_TIMER) += timer-u300.o
obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o
obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o
-obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o
+obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o
obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o
obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o
obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra.c
similarity index 100%
rename from drivers/clocksource/timer-tegra20.c
rename to drivers/clocksource/timer-tegra.c
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 14/25] clocksource/drivers/sysctr: Add nxp system counter timer driver support
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (11 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 13/25] clocksource/drivers/tegra: Rename timer-tegra20.c to timer-tegra.c Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 15/25] clocksource/drivers/arm_arch_timer: Extract elf_hwcap use to arch-helper Daniel Lezcano
` (10 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Bai Ping, Rob Herring, Mark Rutland, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
From: Bai Ping <ping.bai@nxp.com>
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
supports:
- 56-bit counter width (roll-over time greater than 40 years)
- compare frame(64-bit compare value) contains programmable interrupt
generation when compare value <= counter value.
[dlezcano] Fixed over 80 chars length warning
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../bindings/timer/nxp,sysctr-timer.txt | 25 +++
drivers/clocksource/Kconfig | 7 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-sysctr.c | 145 ++++++++++++++++++
4 files changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
create mode 100644 drivers/clocksource/timer-imx-sysctr.c
diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
new file mode 100644
index 000000000000..d57659996d62
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
@@ -0,0 +1,25 @@
+NXP System Counter Module(sys_ctr)
+
+The system counter(sys_ctr) is a programmable system counter which provides
+a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in
+applications where the counter is always powered and support multiple,
+unrelated clocks. The compare frame inside can be used for timer purpose.
+
+Required properties:
+
+- compatible : should be "nxp,sysctr-timer"
+- reg : Specifies the base physical address and size of the comapre
+ frame and the counter control, read & compare.
+- interrupts : should be the first compare frames' interrupt
+- clocks : Specifies the counter clock.
+- clock-names: Specifies the clock's name of this module
+
+Example:
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */
+ clocks = <&clk_8m>;
+ clock-names = "per";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d17a347e813a..e9936992934a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -617,6 +617,13 @@ config CLKSRC_IMX_TPM
Enable this option to use IMX Timer/PWM Module (TPM) timer as
clocksource.
+config TIMER_IMX_SYS_CTR
+ bool "i.MX system counter timer" if COMPILE_TEST
+ select TIMER_OF
+ help
+ Enable this option to use i.MX system counter timer as a
+ clockevent.
+
config CLKSRC_ST_LPC
bool "Low power clocksource found in the LPC" if COMPILE_TEST
select TIMER_OF if OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4145b21eaed3..0939886b305f 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += timer-tango-xtal.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
+obj-$(CONFIG_TIMER_IMX_SYS_CTR) += timer-imx-sysctr.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o
obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
new file mode 100644
index 000000000000..fd7d68066efb
--- /dev/null
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2017-2019 NXP
+
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "timer-of.h"
+
+#define CMP_OFFSET 0x10000
+
+#define CNTCV_LO 0x8
+#define CNTCV_HI 0xc
+#define CMPCV_LO (CMP_OFFSET + 0x20)
+#define CMPCV_HI (CMP_OFFSET + 0x24)
+#define CMPCR (CMP_OFFSET + 0x2c)
+
+#define SYS_CTR_EN 0x1
+#define SYS_CTR_IRQ_MASK 0x2
+
+static void __iomem *sys_ctr_base;
+static u32 cmpcr;
+
+static void sysctr_timer_enable(bool enable)
+{
+ writel(enable ? cmpcr | SYS_CTR_EN : cmpcr, sys_ctr_base + CMPCR);
+}
+
+static void sysctr_irq_acknowledge(void)
+{
+ /*
+ * clear the enable bit(EN =0) will clear
+ * the status bit(ISTAT = 0), then the interrupt
+ * signal will be negated(acknowledged).
+ */
+ sysctr_timer_enable(false);
+}
+
+static inline u64 sysctr_read_counter(void)
+{
+ u32 cnt_hi, tmp_hi, cnt_lo;
+
+ do {
+ cnt_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
+ cnt_lo = readl_relaxed(sys_ctr_base + CNTCV_LO);
+ tmp_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
+ } while (tmp_hi != cnt_hi);
+
+ return ((u64) cnt_hi << 32) | cnt_lo;
+}
+
+static int sysctr_set_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+{
+ u32 cmp_hi, cmp_lo;
+ u64 next;
+
+ sysctr_timer_enable(false);
+
+ next = sysctr_read_counter();
+
+ next += delta;
+
+ cmp_hi = (next >> 32) & 0x00fffff;
+ cmp_lo = next & 0xffffffff;
+
+ writel_relaxed(cmp_hi, sys_ctr_base + CMPCV_HI);
+ writel_relaxed(cmp_lo, sys_ctr_base + CMPCV_LO);
+
+ sysctr_timer_enable(true);
+
+ return 0;
+}
+
+static int sysctr_set_state_oneshot(struct clock_event_device *evt)
+{
+ return 0;
+}
+
+static int sysctr_set_state_shutdown(struct clock_event_device *evt)
+{
+ sysctr_timer_enable(false);
+
+ return 0;
+}
+
+static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+
+ sysctr_irq_acknowledge();
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct timer_of to_sysctr = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
+ .clkevt = {
+ .name = "i.MX system counter timer",
+ .features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ,
+ .set_state_oneshot = sysctr_set_state_oneshot,
+ .set_next_event = sysctr_set_next_event,
+ .set_state_shutdown = sysctr_set_state_shutdown,
+ .rating = 200,
+ },
+ .of_irq = {
+ .handler = sysctr_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+ .of_clk = {
+ .name = "per",
+ },
+};
+
+static void __init sysctr_clockevent_init(void)
+{
+ to_sysctr.clkevt.cpumask = cpumask_of(0);
+
+ clockevents_config_and_register(&to_sysctr.clkevt,
+ timer_of_rate(&to_sysctr),
+ 0xff, 0x7fffffff);
+}
+
+static int __init sysctr_timer_init(struct device_node *np)
+{
+ int ret = 0;
+
+ ret = timer_of_init(np, &to_sysctr);
+ if (ret)
+ return ret;
+
+ sys_ctr_base = timer_of_base(&to_sysctr);
+ cmpcr = readl(sys_ctr_base + CMPCR);
+ cmpcr &= ~SYS_CTR_EN;
+
+ sysctr_clockevent_init();
+
+ return 0;
+}
+TIMER_OF_DECLARE(sysctr_timer, "nxp,sysctr-timer", sysctr_timer_init);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 15/25] clocksource/drivers/arm_arch_timer: Extract elf_hwcap use to arch-helper
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (12 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 14/25] clocksource/drivers/sysctr: Add nxp system counter timer driver support Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 16/25] clocksource/drivers/tegra: Restore timer rate on Tegra210 Daniel Lezcano
` (9 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Andrew Murray, Mark Rutland, Will Deacon,
Marc Zyngier, Russell King, Catalin Marinas,
moderated list:ARM ARCHITECTED TIMER DRIVER
From: Andrew Murray <andrew.murray@arm.com>
Different mechanisms are used to test and set elf_hwcaps between ARM
and ARM64, this results in the use of ifdeferry in this file when
setting/testing for the EVTSTRM hwcap.
Let's improve readability by extracting this to an arch helper.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm/include/asm/arch_timer.h | 10 ++++++++++
arch/arm64/include/asm/arch_timer.h | 13 +++++++++++++
drivers/clocksource/arm_arch_timer.c | 15 ++-------------
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 4b66ecd6be99..99175812d903 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -4,6 +4,7 @@
#include <asm/barrier.h>
#include <asm/errno.h>
+#include <asm/hwcap.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/types.h>
@@ -124,6 +125,15 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
isb();
}
+static inline void arch_timer_set_evtstrm_feature(void)
+{
+ elf_hwcap |= HWCAP_EVTSTRM;
+}
+
+static inline bool arch_timer_have_evtstrm_feature(void)
+{
+ return elf_hwcap & HWCAP_EVTSTRM;
+}
#endif
#endif
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index 50b3ab7ded4f..a847a3ee6cab 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -20,6 +20,7 @@
#define __ASM_ARCH_TIMER_H
#include <asm/barrier.h>
+#include <asm/hwcap.h>
#include <asm/sysreg.h>
#include <linux/bug.h>
@@ -240,4 +241,16 @@ static inline int arch_timer_arch_init(void)
return 0;
}
+static inline void arch_timer_set_evtstrm_feature(void)
+{
+ cpu_set_named_feature(EVTSTRM);
+#ifdef CONFIG_COMPAT
+ compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
+#endif
+}
+
+static inline bool arch_timer_have_evtstrm_feature(void)
+{
+ return cpu_have_named_feature(EVTSTRM);
+}
#endif
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 5c69c9a9a6a4..3c8afcd3444c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -804,14 +804,7 @@ static void arch_timer_evtstrm_enable(int divider)
cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
| ARCH_TIMER_VIRT_EVT_EN;
arch_timer_set_cntkctl(cntkctl);
-#ifdef CONFIG_ARM64
- cpu_set_named_feature(EVTSTRM);
-#else
- elf_hwcap |= HWCAP_EVTSTRM;
-#endif
-#ifdef CONFIG_COMPAT
- compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
-#endif
+ arch_timer_set_evtstrm_feature();
cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
}
@@ -1040,11 +1033,7 @@ static int arch_timer_cpu_pm_notify(struct notifier_block *self,
} else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
-#ifdef CONFIG_ARM64
- if (cpu_have_named_feature(EVTSTRM))
-#else
- if (elf_hwcap & HWCAP_EVTSTRM)
-#endif
+ if (arch_timer_have_evtstrm_feature())
cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
}
return NOTIFY_OK;
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 16/25] clocksource/drivers/tegra: Restore timer rate on Tegra210
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (13 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 15/25] clocksource/drivers/arm_arch_timer: Extract elf_hwcap use to arch-helper Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 17/25] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr Daniel Lezcano
` (8 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
The clocksource rate is initialized only for the first per-CPU clocksource
and then that rate shall be replicated for the rest of clocksource's
because they are initialized manually in the code.
Fixes: 3be2a85a0b61 ("clocksource/drivers/tegra: Support per-CPU timers on all Tegra's")
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index ed1454000ea9..880ba67ca7ee 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -279,6 +279,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
*/
if (tegra20)
cpu_to->of_clk.rate = 1000000;
+ else
+ cpu_to->of_clk.rate = timer_of_rate(to);
cpu_to = per_cpu_ptr(&tegra_to, cpu);
cpu_to->of_base.base = timer_reg_base + base;
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 17/25] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (14 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 16/25] clocksource/drivers/tegra: Restore timer rate on Tegra210 Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period Daniel Lezcano
` (7 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
It was left unnoticed by accident, which means that the code could be
cleaned up a tad more.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 42 ++++++++++++++++++-------------
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index 880ba67ca7ee..f172a57cc5fe 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -218,6 +218,19 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
return TIMER10_IRQ_IDX + cpu;
}
+static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
+ bool tegra20)
+{
+ /*
+ * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
+ * parent clock.
+ */
+ if (tegra20)
+ return 1000000;
+
+ return timer_of_rate(to);
+}
+
static int __init tegra_init_timer(struct device_node *np, bool tegra20,
int rating)
{
@@ -270,32 +283,27 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
+ unsigned long rate = tegra_rate_for_timer(to, tegra20);
unsigned int base = tegra_base_for_cpu(cpu, tegra20);
unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
+ unsigned int irq = irq_of_parse_and_map(np, idx);
- /*
- * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
- * parent clock.
- */
- if (tegra20)
- cpu_to->of_clk.rate = 1000000;
- else
- cpu_to->of_clk.rate = timer_of_rate(to);
-
- cpu_to = per_cpu_ptr(&tegra_to, cpu);
- cpu_to->of_base.base = timer_reg_base + base;
- cpu_to->clkevt.rating = rating;
- cpu_to->clkevt.cpumask = cpumask_of(cpu);
- cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
- if (!cpu_to->clkevt.irq) {
+ if (!irq) {
pr_err("failed to map irq for cpu%d\n", cpu);
ret = -EINVAL;
goto out_irq;
}
+ cpu_to->clkevt.irq = irq;
+ cpu_to->clkevt.rating = rating;
+ cpu_to->clkevt.cpumask = cpumask_of(cpu);
+ cpu_to->of_base.base = timer_reg_base + base;
+ cpu_to->of_clk.rate = rate;
+
irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
- ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
- IRQF_TIMER | IRQF_NOBALANCING,
+
+ ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
cpu_to->clkevt.name, &cpu_to->clkevt);
if (ret) {
pr_err("failed to set up irq for cpu%d: %d\n",
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (15 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 17/25] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 19/25] clocksource/drivers/tegra: Drop unneeded typecasting in one place Daniel Lezcano
` (6 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
The of_clk structure has a period field that is set up initially by
timer_of_clk_init(), that period value need to be adjusted for a case of
TIMER1-9 that are running at a fixed rate that doesn't match the clock's
rate. Note that the period value is currently used only by some of the
clocksource drivers internally and hence this is just a minor cleanup
change that doesn't fix anything.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index f172a57cc5fe..41257f89a216 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -73,9 +73,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+ unsigned long period = timer_of_period(to_timer_of(evt));
- writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
- ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+ writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
reg_base + TIMER_PTV);
return 0;
@@ -299,6 +299,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
cpu_to->clkevt.rating = rating;
cpu_to->clkevt.cpumask = cpumask_of(cpu);
cpu_to->of_base.base = timer_reg_base + base;
+ cpu_to->of_clk.period = rate / HZ;
cpu_to->of_clk.rate = rate;
irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 19/25] clocksource/drivers/tegra: Drop unneeded typecasting in one place
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (16 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 20/25] clocksource/drivers/tegra: Add verbose definition for 1MHz constant Daniel Lezcano
` (5 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
There is no need to cast void because kernel allows to do that without
a warning message from a compiler.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index 41257f89a216..f7a09d88dacb 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -83,7 +83,7 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt)
static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
{
- struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+ struct clock_event_device *evt = dev_id;
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 20/25] clocksource/drivers/tegra: Add verbose definition for 1MHz constant
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (17 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 19/25] clocksource/drivers/tegra: Drop unneeded typecasting in one place Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 21/25] clocksource/drivers/tegra: Restore base address before cleanup Daniel Lezcano
` (4 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Convert all 1MHz literals to a verbose constant for better readability.
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index f7a09d88dacb..cc90f22c559b 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -46,6 +46,8 @@
#define TIMER1_IRQ_IDX 0
#define TIMER10_IRQ_IDX 10
+#define TIMER_1MHz 1000000
+
static u32 usec_config;
static void __iomem *timer_reg_base;
@@ -160,7 +162,7 @@ static unsigned long tegra_delay_timer_read_counter_long(void)
static struct delay_timer tegra_delay_timer = {
.read_current_timer = tegra_delay_timer_read_counter_long,
- .freq = 1000000,
+ .freq = TIMER_1MHz,
};
#endif
@@ -226,7 +228,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
* parent clock.
*/
if (tegra20)
- return 1000000;
+ return TIMER_1MHz;
return timer_of_rate(to);
}
@@ -315,11 +317,11 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
}
}
- sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+ sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
- "timer_us", 1000000,
- 300, 32, clocksource_mmio_readl_up);
+ "timer_us", TIMER_1MHz, 300, 32,
+ clocksource_mmio_readl_up);
if (ret)
pr_err("failed to register clocksource: %d\n", ret);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 21/25] clocksource/drivers/tegra: Restore base address before cleanup
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (18 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 20/25] clocksource/drivers/tegra: Add verbose definition for 1MHz constant Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 22/25] clocksource/drivers/tegra: Cycles can't be 0 Daniel Lezcano
` (3 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
We're adjusting the timer's base for each per-CPU timer to point to the
actual start of the timer since device-tree defines a compound registers
range that includes all of the timers. In this case the original base
need to be restore before calling iounmap to unmap the proper address.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index cc90f22c559b..8e70f38f1898 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -347,6 +347,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
irq_dispose_mapping(cpu_to->clkevt.irq);
}
}
+
+ to->of_base.base = timer_reg_base;
out:
timer_of_cleanup(to);
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 22/25] clocksource/drivers/tegra: Cycles can't be 0
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (19 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 21/25] clocksource/drivers/tegra: Restore base address before cleanup Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 23/25] clocksource/drivers/tegra: Set up maximum-ticks limit properly Daniel Lezcano
` (2 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after
one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks
are defined by clockevents_config_and_register(min, max) invocation and
the min value is set to 1 tick. Hence "cycles" value can't ever be 0,
unless it's a bug in clocksource core.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index 8e70f38f1898..a907e71065bd 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -56,9 +56,16 @@ static int tegra_timer_set_next_event(unsigned long cycles,
{
void __iomem *reg_base = timer_of_base(to_timer_of(evt));
- writel_relaxed(TIMER_PTV_EN |
- ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
- reg_base + TIMER_PTV);
+ /*
+ * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
+ * fire after one tick if 0 is loaded.
+ *
+ * The minimum and maximum numbers of oneshot ticks are defined
+ * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
+ * below in the code. Hence the cycles (ticks) can't be outside of
+ * a range supportable by hardware.
+ */
+ writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 23/25] clocksource/drivers/tegra: Set up maximum-ticks limit properly
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (20 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 22/25] clocksource/drivers/tegra: Cycles can't be 0 Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 24/25] clocksource/drivers/davinci: Add support for clockevents Daniel Lezcano
2019-06-26 14:46 ` [PATCH 25/25] clocksource/drivers/davinci: Add support for clocksource Daniel Lezcano
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx
Cc: linux-kernel, Dmitry Osipenko, Jon Hunter, Thierry Reding,
Thierry Reding, open list:TEGRA ARCHITECTURE SUPPORT
From: Dmitry Osipenko <digetx@gmail.com>
Tegra's timer has 29 bits for the counter and for the "load" register
which sets counter to a load-value. The counter's value is lower than
the actual value by 1 because it starts to decrement after one tick,
hence the maximum number of ticks that hardware can handle equals to
29 bits + 1.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-tegra.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index a907e71065bd..e9635c25eef4 100644
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -139,9 +139,17 @@ static int tegra_timer_setup(unsigned int cpu)
irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
enable_irq(to->clkevt.irq);
+ /*
+ * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
+ * fire after one tick if 0 is loaded and thus minimum number of
+ * ticks is 1. In result both of the clocksource's tick limits are
+ * higher than a minimum and maximum that hardware register can
+ * take by 1, this is then taken into account by set_next_event
+ * callback.
+ */
clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
1, /* min */
- 0x1fffffff); /* 29 bits */
+ 0x1fffffff + 1); /* max 29 bits + 1 */
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 24/25] clocksource/drivers/davinci: Add support for clockevents
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (21 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 23/25] clocksource/drivers/tegra: Set up maximum-ticks limit properly Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
2019-06-26 14:46 ` [PATCH 25/25] clocksource/drivers/davinci: Add support for clocksource Daniel Lezcano
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx; +Cc: linux-kernel, Bartosz Golaszewski
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Currently the clocksource and clockevent support for davinci platforms
lives in mach-davinci. It hard-codes many things, uses global variables,
implements functionalities unused by any platform and has code fragments
scattered across many (often unrelated) files.
Implement a new, modern and simplified timer driver and put it into
drivers/clocksource. We still need to support legacy board files so
export a config structure and a function that allows machine code to
register the timer.
The timer we're using is 64-bit but can be programmed in dual 32-bit
mode (both chained and unchained).
On all davinci SoCs except for da830 we're using both halves. Lower half
for clockevents and upper half for clocksource. On da830 we're using the
lower half for both with the help of a compare register.
This patch contains the core code and support for clockevent. The
clocksource code will be included in a subsequent patch.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 5 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-davinci.c | 284 ++++++++++++++++++++++++++++
include/clocksource/timer-davinci.h | 44 +++++
4 files changed, 334 insertions(+)
create mode 100644 drivers/clocksource/timer-davinci.c
create mode 100644 include/clocksource/timer-davinci.h
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e9936992934a..5e9317dc3d39 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -43,6 +43,11 @@ config BCM_KONA_TIMER
help
Enables the support for the BCM Kona mobile timer driver.
+config DAVINCI_TIMER
+ bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST
+ help
+ Enables the support for the TI DaVinci timer driver.
+
config DIGICOLOR_TIMER
bool "Digicolor timer driver" if COMPILE_TEST
select CLKSRC_MMIO
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 0939886b305f..5582252efb31 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
+obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
new file mode 100644
index 000000000000..246a5564495d
--- /dev/null
+++ b/drivers/clocksource/timer-davinci.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * TI DaVinci clocksource driver
+ *
+ * Copyright (C) 2019 Texas Instruments
+ * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ * (with tiny parts adopted from code by Kevin Hilman <khilman@baylibre.com>)
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+
+#include <clocksource/timer-davinci.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt "\n", __func__
+
+#define DAVINCI_TIMER_REG_TIM12 0x10
+#define DAVINCI_TIMER_REG_TIM34 0x14
+#define DAVINCI_TIMER_REG_PRD12 0x18
+#define DAVINCI_TIMER_REG_PRD34 0x1c
+#define DAVINCI_TIMER_REG_TCR 0x20
+#define DAVINCI_TIMER_REG_TGCR 0x24
+
+#define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)
+#define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)
+#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2)
+#define DAVINCI_TIMER_UNRESET GENMASK(1, 0)
+
+#define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)
+#define DAVINCI_TIMER_ENAMODE_DISABLED 0x00
+#define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0)
+#define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1)
+
+#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6
+#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22
+
+#define DAVINCI_TIMER_MIN_DELTA 0x01
+#define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
+
+#define DAVINCI_TIMER_TGCR_DEFAULT \
+ (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
+
+struct davinci_clockevent {
+ struct clock_event_device dev;
+ void __iomem *base;
+ unsigned int cmp_off;
+};
+
+static struct davinci_clockevent *
+to_davinci_clockevent(struct clock_event_device *clockevent)
+{
+ return container_of(clockevent, struct davinci_clockevent, dev);
+}
+
+static unsigned int
+davinci_clockevent_read(struct davinci_clockevent *clockevent,
+ unsigned int reg)
+{
+ return readl_relaxed(clockevent->base + reg);
+}
+
+static void davinci_clockevent_write(struct davinci_clockevent *clockevent,
+ unsigned int reg, unsigned int val)
+{
+ writel_relaxed(val, clockevent->base + reg);
+}
+
+static void davinci_tim12_shutdown(void __iomem *base)
+{
+ unsigned int tcr;
+
+ tcr = DAVINCI_TIMER_ENAMODE_DISABLED <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
+ /*
+ * This function is only ever called if we're using both timer
+ * halves. In this case TIM34 runs in periodic mode and we must
+ * not modify it.
+ */
+ tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
+
+ writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
+}
+
+static void davinci_tim12_set_oneshot(void __iomem *base)
+{
+ unsigned int tcr;
+
+ tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
+ /* Same as above. */
+ tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
+
+ writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
+}
+
+static int davinci_clockevent_shutdown(struct clock_event_device *dev)
+{
+ struct davinci_clockevent *clockevent;
+
+ clockevent = to_davinci_clockevent(dev);
+
+ davinci_tim12_shutdown(clockevent->base);
+
+ return 0;
+}
+
+static int davinci_clockevent_set_oneshot(struct clock_event_device *dev)
+{
+ struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
+
+ davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
+
+ davinci_tim12_set_oneshot(clockevent->base);
+
+ return 0;
+}
+
+static int
+davinci_clockevent_set_next_event_std(unsigned long cycles,
+ struct clock_event_device *dev)
+{
+ struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
+
+ davinci_clockevent_shutdown(dev);
+
+ davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
+ davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles);
+
+ davinci_clockevent_set_oneshot(dev);
+
+ return 0;
+}
+
+static int
+davinci_clockevent_set_next_event_cmp(unsigned long cycles,
+ struct clock_event_device *dev)
+{
+ struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
+ unsigned int curr_time;
+
+ curr_time = davinci_clockevent_read(clockevent,
+ DAVINCI_TIMER_REG_TIM12);
+ davinci_clockevent_write(clockevent,
+ clockevent->cmp_off, curr_time + cycles);
+
+ return 0;
+}
+
+static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
+{
+ struct davinci_clockevent *clockevent = data;
+
+ if (!clockevent_state_oneshot(&clockevent->dev))
+ davinci_tim12_shutdown(clockevent->base);
+
+ clockevent->dev.event_handler(&clockevent->dev);
+
+ return IRQ_HANDLED;
+}
+
+static void davinci_timer_init(void __iomem *base)
+{
+ /* Set clock to internal mode and disable it. */
+ writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
+ /*
+ * Reset both 32-bit timers, set no prescaler for timer 34, set the
+ * timer to dual 32-bit unchained mode, unreset both 32-bit timers.
+ */
+ writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
+ base + DAVINCI_TIMER_REG_TGCR);
+ /* Init both counters to zero. */
+ writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
+ writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
+}
+
+int __init davinci_timer_register(struct clk *clk,
+ const struct davinci_timer_cfg *timer_cfg)
+{
+ struct davinci_clockevent *clockevent;
+ unsigned int tick_rate;
+ void __iomem *base;
+ int rv;
+
+ rv = clk_prepare_enable(clk);
+ if (rv) {
+ pr_err("Unable to prepare and enable the timer clock");
+ return rv;
+ }
+
+ if (!request_mem_region(timer_cfg->reg.start,
+ resource_size(&timer_cfg->reg),
+ "davinci-timer")) {
+ pr_err("Unable to request memory region");
+ return -EBUSY;
+ }
+
+ base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
+ if (!base) {
+ pr_err("Unable to map the register range");
+ return -ENOMEM;
+ }
+
+ davinci_timer_init(base);
+ tick_rate = clk_get_rate(clk);
+
+ clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL | __GFP_NOFAIL);
+ if (!clockevent) {
+ pr_err("Error allocating memory for clockevent data");
+ return -ENOMEM;
+ }
+
+ clockevent->dev.name = "tim12";
+ clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
+ clockevent->dev.cpumask = cpumask_of(0);
+ clockevent->base = base;
+
+ if (timer_cfg->cmp_off) {
+ clockevent->cmp_off = timer_cfg->cmp_off;
+ clockevent->dev.set_next_event =
+ davinci_clockevent_set_next_event_cmp;
+ } else {
+ clockevent->dev.set_next_event =
+ davinci_clockevent_set_next_event_std;
+ clockevent->dev.set_state_oneshot =
+ davinci_clockevent_set_oneshot;
+ clockevent->dev.set_state_shutdown =
+ davinci_clockevent_shutdown;
+ }
+
+ rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
+ davinci_timer_irq_timer, IRQF_TIMER,
+ "clockevent/tim12", clockevent);
+ if (rv) {
+ pr_err("Unable to request the clockevent interrupt");
+ return rv;
+ }
+
+ clockevents_config_and_register(&clockevent->dev, tick_rate,
+ DAVINCI_TIMER_MIN_DELTA,
+ DAVINCI_TIMER_MAX_DELTA);
+
+ return 0;
+}
+
+static int __init of_davinci_timer_register(struct device_node *np)
+{
+ struct davinci_timer_cfg timer_cfg = { };
+ struct clk *clk;
+ int rv;
+
+ rv = of_address_to_resource(np, 0, &timer_cfg.reg);
+ if (rv) {
+ pr_err("Unable to get the register range for timer");
+ return rv;
+ }
+
+ rv = of_irq_to_resource_table(np, timer_cfg.irq,
+ DAVINCI_TIMER_NUM_IRQS);
+ if (rv != DAVINCI_TIMER_NUM_IRQS) {
+ pr_err("Unable to get the interrupts for timer");
+ return rv;
+ }
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk)) {
+ pr_err("Unable to get the timer clock");
+ return PTR_ERR(clk);
+ }
+
+ rv = davinci_timer_register(clk, &timer_cfg);
+ if (rv)
+ clk_put(clk);
+
+ return rv;
+}
+TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);
diff --git a/include/clocksource/timer-davinci.h b/include/clocksource/timer-davinci.h
new file mode 100644
index 000000000000..1dcc1333fbc8
--- /dev/null
+++ b/include/clocksource/timer-davinci.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * TI DaVinci clocksource driver
+ *
+ * Copyright (C) 2019 Texas Instruments
+ * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ */
+
+#ifndef __TIMER_DAVINCI_H__
+#define __TIMER_DAVINCI_H__
+
+#include <linux/clk.h>
+#include <linux/ioport.h>
+
+enum {
+ DAVINCI_TIMER_CLOCKEVENT_IRQ,
+ DAVINCI_TIMER_CLOCKSOURCE_IRQ,
+ DAVINCI_TIMER_NUM_IRQS,
+};
+
+/**
+ * struct davinci_timer_cfg - davinci clocksource driver configuration struct
+ * @reg: register range resource
+ * @irq: clockevent and clocksource interrupt resources
+ * @cmp_off: if set - it specifies the compare register used for clockevent
+ *
+ * Note: if the compare register is specified, the driver will use the bottom
+ * clock half for both clocksource and clockevent and the compare register
+ * to generate event irqs. The user must supply the correct compare register
+ * interrupt number.
+ *
+ * This is only used by da830 the DSP of which uses the top half. The timer
+ * driver still configures the top half to run in free-run mode.
+ */
+struct davinci_timer_cfg {
+ struct resource reg;
+ struct resource irq[DAVINCI_TIMER_NUM_IRQS];
+ unsigned int cmp_off;
+};
+
+int __init davinci_timer_register(struct clk *clk,
+ const struct davinci_timer_cfg *data);
+
+#endif /* __TIMER_DAVINCI_H__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 25/25] clocksource/drivers/davinci: Add support for clocksource
2019-06-26 14:46 ` [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Daniel Lezcano
` (22 preceding siblings ...)
2019-06-26 14:46 ` [PATCH 24/25] clocksource/drivers/davinci: Add support for clockevents Daniel Lezcano
@ 2019-06-26 14:46 ` Daniel Lezcano
23 siblings, 0 replies; 26+ messages in thread
From: Daniel Lezcano @ 2019-06-26 14:46 UTC (permalink / raw)
To: tglx; +Cc: linux-kernel, Bartosz Golaszewski
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Extend the davinci-timer driver to also register a clock source.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-davinci.c | 85 +++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
index 246a5564495d..62745c962049 100644
--- a/drivers/clocksource/timer-davinci.c
+++ b/drivers/clocksource/timer-davinci.c
@@ -43,6 +43,8 @@
#define DAVINCI_TIMER_MIN_DELTA 0x01
#define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
+#define DAVINCI_TIMER_CLKSRC_BITS 32
+
#define DAVINCI_TIMER_TGCR_DEFAULT \
(DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
@@ -52,6 +54,16 @@ struct davinci_clockevent {
unsigned int cmp_off;
};
+/*
+ * This must be globally accessible by davinci_timer_read_sched_clock(), so
+ * let's keep it here.
+ */
+static struct {
+ struct clocksource dev;
+ void __iomem *base;
+ unsigned int tim_off;
+} davinci_clocksource;
+
static struct davinci_clockevent *
to_davinci_clockevent(struct clock_event_device *clockevent)
{
@@ -166,6 +178,53 @@ static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
return IRQ_HANDLED;
}
+static u64 notrace davinci_timer_read_sched_clock(void)
+{
+ return readl_relaxed(davinci_clocksource.base +
+ davinci_clocksource.tim_off);
+}
+
+static u64 davinci_clocksource_read(struct clocksource *dev)
+{
+ return davinci_timer_read_sched_clock();
+}
+
+/*
+ * Standard use-case: we're using tim12 for clockevent and tim34 for
+ * clocksource. The default is making the former run in oneshot mode
+ * and the latter in periodic mode.
+ */
+static void davinci_clocksource_init_tim34(void __iomem *base)
+{
+ int tcr;
+
+ tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
+ tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
+
+ writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
+ writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
+ writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
+}
+
+/*
+ * Special use-case on da830: the DSP may use tim34. We're using tim12 for
+ * both clocksource and clockevent. We set tim12 to periodic and don't touch
+ * tim34.
+ */
+static void davinci_clocksource_init_tim12(void __iomem *base)
+{
+ unsigned int tcr;
+
+ tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
+
+ writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
+ writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
+ writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
+}
+
static void davinci_timer_init(void __iomem *base)
{
/* Set clock to internal mode and disable it. */
@@ -247,6 +306,32 @@ int __init davinci_timer_register(struct clk *clk,
DAVINCI_TIMER_MIN_DELTA,
DAVINCI_TIMER_MAX_DELTA);
+ davinci_clocksource.dev.rating = 300;
+ davinci_clocksource.dev.read = davinci_clocksource_read;
+ davinci_clocksource.dev.mask =
+ CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
+ davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+ davinci_clocksource.base = base;
+
+ if (timer_cfg->cmp_off) {
+ davinci_clocksource.dev.name = "tim12";
+ davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12;
+ davinci_clocksource_init_tim12(base);
+ } else {
+ davinci_clocksource.dev.name = "tim34";
+ davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34;
+ davinci_clocksource_init_tim34(base);
+ }
+
+ rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
+ if (rv) {
+ pr_err("Unable to register clocksource");
+ return rv;
+ }
+
+ sched_clock_register(davinci_timer_read_sched_clock,
+ DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 26+ messages in thread