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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Alan Kao <alankao@andestech.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup.patel@wdc.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	devicetree@vger.kernel.org, Enrico Weigelt <info@metux.net>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Johan Hovold <johan@kernel.org>,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v4 4/4] dt-bindings: Update the riscv,isa string description
Date: Fri,  2 Aug 2019 21:27:23 -0700	[thread overview]
Message-ID: <20190803042723.7163-5-atish.patra@wdc.com> (raw)
In-Reply-To: <20190803042723.7163-1-atish.patra@wdc.com>

Since the RISC-V specification states that ISA description strings are
case-insensitive, there's no functional difference between mixed-case,
upper-case, and lower-case ISA strings. Thus, to simplify parsing,
specify that the letters present in "riscv,isa" must be all lowercase.

Suggested-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c899111aa5e3..9d3fe6aada2b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -50,6 +50,10 @@ properties:
       User-Level ISA document, available from
       https://riscv.org/specifications/
 
+      While the isa strings in ISA specification are case
+      insensitive, letters in the riscv,isa string must be all
+      lowercase to simplify parsing.
+
   timebase-frequency:
     type: integer
     minimum: 1
-- 
2.21.0


  parent reply	other threads:[~2019-08-03  4:27 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-03  4:27 [PATCH v4 0/4] Miscellaneous fixes Atish Patra
2019-08-03  4:27 ` [PATCH v4 1/4] RISC-V: Remove per cpu clocksource Atish Patra
2019-08-06 21:37   ` Paul Walmsley
2019-08-07  8:04     ` Daniel Lezcano
2019-08-03  4:27 ` [PATCH v4 2/4] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra
2019-08-06 21:54   ` Paul Walmsley
2019-08-07  4:12     ` Anup Patel
2019-08-07  6:51   ` Christoph Hellwig
2019-08-07  6:55     ` Anup Patel
2019-08-03  4:27 ` [PATCH v4 3/4] RISC-V: Fix unsupported isa string info Atish Patra
2019-08-03  4:27 ` Atish Patra [this message]
2019-08-06 21:43   ` [PATCH v4 4/4] dt-bindings: Update the riscv,isa string description Paul Walmsley

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