[PATCH 0/3] x86: cpu: Add new Airmont CPU model

[PATCH 0/3] x86: cpu: Add new Airmont CPU model

[Rahul Tanwar]

Intel Atom CPU based Lightning Mountain(LGM) network processor SoC has recently
taped out. Although the Atom CPU used in LGM is based upon Airmont uArch but it
has a few differences. Its a new variant of Atom Airmont cpu model.

This series of patches adds support for this new CPU model.

Patches are baselined upon Linux 5.3-rc4 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core

Patch 1 replaces existing direct values usage with constant definitions when
access CPU models.

Patch 2 adds a constant definition for the new Atom CPU model.

Patch 3 updates capabilities & vulnerabilities applicable for this new CPU model.


Rahul Tanwar (3):
  x86: cpu: Use constant definitions for CPU type
  x86: cpu: Add new Intel Atom CPU type
  x86: arch: Add arch support for new Intel Atom CPU

 arch/x86/include/asm/intel-family.h | 1 +
 arch/x86/kernel/cpu/common.c        | 1 +
 arch/x86/kernel/cpu/intel.c         | 7 ++++---
 arch/x86/kernel/tsc_msr.c           | 5 +++++
 4 files changed, 11 insertions(+), 3 deletions(-)

-- 
2.11.0

[PATCH 1/3] x86: cpu: Use constant definitions for CPU type

[Rahul Tanwar]

This patch replaces direct values usage with constant definitions usage
when access CPU models.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
---
 arch/x86/kernel/cpu/intel.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 8d6d92ebeb54..0419fba1ea56 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -265,9 +265,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
 	if (c->x86 == 6) {
 		switch (c->x86_model) {
-		case 0x27:	/* Penwell */
-		case 0x35:	/* Cloverview */
-		case 0x4a:	/* Merrifield */
+		case INTEL_FAM6_ATOM_SALTWELL_MID:	/* Penwell */
+		case INTEL_FAM6_ATOM_SALTWELL_TABLET:	/* Cloverview */
+		case INTEL_FAM6_ATOM_SILVERMONT_MID:	/* Merrifield */
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
-- 
2.11.0

[PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Rahul Tanwar]

This patch adds a new variant of Intel Atom Airmont CPU model used in a
network processor SoC named Lightning Mountain.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
 arch/x86/include/asm/intel-family.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 0278aa66ef62..cbbb8250370f 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -73,6 +73,7 @@
 
 #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
 #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
+#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
 
 #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
 #define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
-- 
2.11.0

[PATCH 3/3] x86: arch: Add arch support for new Intel Atom CPU

[Rahul Tanwar]

This patch adds basic arch support for a new variant of Intel Atom CPU
model used in a network processor SoC named Lightning Mountain.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
 arch/x86/kernel/cpu/common.c | 1 +
 arch/x86/kernel/cpu/intel.c  | 1 +
 arch/x86/kernel/tsc_msr.c    | 5 +++++
 3 files changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5cc2d51cc25e..c6b4a578b280 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 	VULNWL_INTEL(CORE_YONAH,		NO_SSB),
 
 	VULNWL_INTEL(ATOM_AIRMONT_MID,		NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+	VULNWL_INTEL(ATOM_AIRMONT_NP,		NO_L1TF | NO_SWAPGS),
 
 	VULNWL_INTEL(ATOM_GOLDMONT,		NO_MDS | NO_L1TF | NO_SWAPGS),
 	VULNWL_INTEL(ATOM_GOLDMONT_X,		NO_MDS | NO_L1TF | NO_SWAPGS),
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0419fba1ea56..e989a8429390 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		case INTEL_FAM6_ATOM_SALTWELL_MID:	/* Penwell */
 		case INTEL_FAM6_ATOM_SALTWELL_TABLET:	/* Cloverview */
 		case INTEL_FAM6_ATOM_SILVERMONT_MID:	/* Merrifield */
+		case INTEL_FAM6_ATOM_AIRMONT_NP:	/* Lightning Mountain */
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8..e0cbe4f2af49 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
 	1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
 };
 
+static const struct freq_desc freq_desc_lgm = {
+	1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
 static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
 	INTEL_CPU_FAM6(ATOM_SALTWELL_MID,	freq_desc_pnw),
 	INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET,	freq_desc_clv),
@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
 	INTEL_CPU_FAM6(ATOM_SILVERMONT_MID,	freq_desc_tng),
 	INTEL_CPU_FAM6(ATOM_AIRMONT,		freq_desc_cht),
 	INTEL_CPU_FAM6(ATOM_AIRMONT_MID,	freq_desc_ann),
+	INTEL_CPU_FAM6(ATOM_AIRMONT_NP,		freq_desc_lgm),
 	{}
 };
 
-- 
2.11.0

Re: [PATCH 1/3] x86: cpu: Use constant definitions for CPU type

[Thomas Gleixner]

Rahul,

On Thu, 15 Aug 2019, Rahul Tanwar wrote:

Please use the proper prefix for your patches. x86 uses

x86/subsystem: not x86: subsystem:

> This patch replaces direct values usage with constant definitions usage
> when access CPU models.

Please do not use 'This patch'. We already know that this is a patch
otherwise you wouldn't have sent it with [PATCH] on the subject line,
right?

See Documentation/process/submitting-patches.rst and search for 'This
patch'.

> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> ---
>  arch/x86/kernel/cpu/intel.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 8d6d92ebeb54..0419fba1ea56 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -265,9 +265,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
>  	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
>  	if (c->x86 == 6) {
>  		switch (c->x86_model) {
> -		case 0x27:	/* Penwell */
> -		case 0x35:	/* Cloverview */
> -		case 0x4a:	/* Merrifield */
> +		case INTEL_FAM6_ATOM_SALTWELL_MID:	/* Penwell */
> +		case INTEL_FAM6_ATOM_SALTWELL_TABLET:	/* Cloverview */
> +		case INTEL_FAM6_ATOM_SILVERMONT_MID:	/* Merrifield */

Are these comments really still useful now that the defines are used? I
don't think so.

Thanks,

	tglx

Re: [PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Borislav Petkov]

On Thu, Aug 15, 2019 at 05:46:46PM +0800, Rahul Tanwar wrote:
> This patch adds a new variant of Intel Atom Airmont CPU model used in a
> network processor SoC named Lightning Mountain.
> 
> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> ---
>  arch/x86/include/asm/intel-family.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
> index 0278aa66ef62..cbbb8250370f 100644
> --- a/arch/x86/include/asm/intel-family.h
> +++ b/arch/x86/include/asm/intel-family.h
> @@ -73,6 +73,7 @@
>  
>  #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
>  #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
> +#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
>  
>  #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
>  #define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
> -- 

Also, in addition to what Thomas said, due to the fact that all the
different groups within Intel are sending patches with model names,
please synchronize that model naming and patch sending with Tony from
now on:

https://git.kernel.org/tip/5ed1c835ed8b522ce25071cc2d56a9a09bd5b59e

He'll document the naming scheme and pay attention to what goes where so
make sure you CC him, talk to him or have him in the loop, in general.

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH 1/3] x86: cpu: Use constant definitions for CPU type

[Tanwar, Rahul]

Hi Thomas,


Thanks for your comments.


On 15/8/2019 6:31 PM, Thomas Gleixner wrote:
> Rahul,
>
> On Thu, 15 Aug 2019, Rahul Tanwar wrote:
>
> Please use the proper prefix for your patches. x86 uses
>
> x86/subsystem: not x86: subsystem:


Well noted.


>> This patch replaces direct values usage with constant definitions usage
>> when access CPU models.
> Please do not use 'This patch'. We already know that this is a patch
> otherwise you wouldn't have sent it with [PATCH] on the subject line,
> right?
>
> See Documentation/process/submitting-patches.rst and search for 'This
> patch'.


Well noted.


>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
>> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
>> ---
>>   arch/x86/kernel/cpu/intel.c | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
>> index 8d6d92ebeb54..0419fba1ea56 100644
>> --- a/arch/x86/kernel/cpu/intel.c
>> +++ b/arch/x86/kernel/cpu/intel.c
>> @@ -265,9 +265,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
>>   	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
>>   	if (c->x86 == 6) {
>>   		switch (c->x86_model) {
>> -		case 0x27:	/* Penwell */
>> -		case 0x35:	/* Cloverview */
>> -		case 0x4a:	/* Merrifield */
>> +		case INTEL_FAM6_ATOM_SALTWELL_MID:	/* Penwell */
>> +		case INTEL_FAM6_ATOM_SALTWELL_TABLET:	/* Cloverview */
>> +		case INTEL_FAM6_ATOM_SILVERMONT_MID:	/* Merrifield */
> Are these comments really still useful now that the defines are used? I
> don't think so.


Agree that these comments can be removed here. These comments are useful to

associate the CPU model with the product name. But, i think, the right 
place to have

these comments is intel-family.h. I will remove these comments from here 
in V2.


Regards,

Rahul

Re: [PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Tanwar, Rahul]

Hi Boris,

Well noted, will have Tony in loop from now on. Thanks.

Regards,

Rahul

On 15/8/2019 8:22 PM, Borislav Petkov wrote:
> On Thu, Aug 15, 2019 at 05:46:46PM +0800, Rahul Tanwar wrote:
>> This patch adds a new variant of Intel Atom Airmont CPU model used in a
>> network processor SoC named Lightning Mountain.
>>
>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
>> ---
>>   arch/x86/include/asm/intel-family.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
>> index 0278aa66ef62..cbbb8250370f 100644
>> --- a/arch/x86/include/asm/intel-family.h
>> +++ b/arch/x86/include/asm/intel-family.h
>> @@ -73,6 +73,7 @@
>>   
>>   #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
>>   #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
>> +#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
>>   
>>   #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
>>   #define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
>> -- 
> Also, in addition to what Thomas said, due to the fact that all the
> different groups within Intel are sending patches with model names,
> please synchronize that model naming and patch sending with Tony from
> now on:
>
> https://git.kernel.org/tip/5ed1c835ed8b522ce25071cc2d56a9a09bd5b59e
>
> He'll document the naming scheme and pay attention to what goes where so
> make sure you CC him, talk to him or have him in the loop, in general.
>
> Thx.
>

Re: [PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Borislav Petkov]

On Fri, Aug 16, 2019 at 11:22:16AM +0800, Tanwar, Rahul wrote:
> 
> Hi Boris,
> 
> Well noted, will have Tony in loop from now on. Thanks.

Ok.

Now to another question: you see how I put my reply to the previous mail
*below* the quoted text. Why is yours ontop? Why not put it after mine
since you're replying to it, like it is usually done on the mailing
lists and thus not confuse the reading order?

All I'm trying to say is, please do not top-post.

Thanks!

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Tanwar, Rahul]

On 16/8/2019 2:43 PM, Borislav Petkov wrote:
> Now to another question: you see how I put my reply to the previous mail
> *below* the quoted text. Why is yours ontop? Why not put it after mine
> since you're replying to it, like it is usually done on the mailing
> lists and thus not confuse the reading order?
>
> All I'm trying to say is, please do not top-post.

So sorry for missing out on this point. Will always keep in mind from 
now on.


Regards,

Rahul

Re: [PATCH 2/3] x86: cpu: Add new Intel Atom CPU type

[Borislav Petkov]

On Fri, Aug 16, 2019 at 03:25:51PM +0800, Tanwar, Rahul wrote:
> 
> On 16/8/2019 2:43 PM, Borislav Petkov wrote:
> > Now to another question: you see how I put my reply to the previous mail
> > *below* the quoted text. Why is yours ontop? Why not put it after mine
> > since you're replying to it, like it is usually done on the mailing
> > lists and thus not confuse the reading order?
> > 
> > All I'm trying to say is, please do not top-post.
> 
> So sorry for missing out on this point. Will always keep in mind from now
> on.

Thanks!

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.