* [PATCH v4 1/4] vesnin: add wdt2 section with alt-boot option
2019-08-28 10:23 [PATCH v4 0/4] add dual-boot support Ivan Mikhaylov
@ 2019-08-28 10:23 ` Ivan Mikhaylov
2019-08-28 10:24 ` [PATCH v4 2/4] vesnin: add secondary SPI flash chip Ivan Mikhaylov
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Ivan Mikhaylov @ 2019-08-28 10:23 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Joel Stanley, Andrew Jeffery, linux-watchdog, linux-arm-kernel,
linux-aspeed, linux-kernel, Alexander Amelkin, openbmc,
Rob Herring, Mark Rutland, devicetree, Ivan Mikhaylov
Adds wdt2 section with 'alt-boot' option into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 0b9e29c3212e..2ee26c86a32e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -222,3 +222,7 @@
&vuart {
status = "okay";
};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 2/4] vesnin: add secondary SPI flash chip
2019-08-28 10:23 [PATCH v4 0/4] add dual-boot support Ivan Mikhaylov
2019-08-28 10:23 ` [PATCH v4 1/4] vesnin: add wdt2 section with alt-boot option Ivan Mikhaylov
@ 2019-08-28 10:24 ` Ivan Mikhaylov
2019-08-28 10:24 ` [PATCH v4 3/4] watchdog/aspeed: add support for dual boot Ivan Mikhaylov
2019-08-28 10:24 ` [PATCH v4 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot Ivan Mikhaylov
3 siblings, 0 replies; 7+ messages in thread
From: Ivan Mikhaylov @ 2019-08-28 10:24 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Joel Stanley, Andrew Jeffery, linux-watchdog, linux-arm-kernel,
linux-aspeed, linux-kernel, Alexander Amelkin, openbmc,
Rob Herring, Mark Rutland, devicetree, Ivan Mikhaylov
Adds secondary SPI flash chip into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 2ee26c86a32e..db4cc3df61ce 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -81,6 +81,14 @@
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
+
+ flash@1 {
+ status = "okay";
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ label = "alt";
+ };
};
&spi {
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 3/4] watchdog/aspeed: add support for dual boot
2019-08-28 10:23 [PATCH v4 0/4] add dual-boot support Ivan Mikhaylov
2019-08-28 10:23 ` [PATCH v4 1/4] vesnin: add wdt2 section with alt-boot option Ivan Mikhaylov
2019-08-28 10:24 ` [PATCH v4 2/4] vesnin: add secondary SPI flash chip Ivan Mikhaylov
@ 2019-08-28 10:24 ` Ivan Mikhaylov
2019-08-31 15:01 ` Guenter Roeck
2019-08-28 10:24 ` [PATCH v4 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot Ivan Mikhaylov
3 siblings, 1 reply; 7+ messages in thread
From: Ivan Mikhaylov @ 2019-08-28 10:24 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Joel Stanley, Andrew Jeffery, linux-watchdog, linux-arm-kernel,
linux-aspeed, linux-kernel, Alexander Amelkin, openbmc,
Rob Herring, Mark Rutland, devicetree, Ivan Mikhaylov
Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
to clear out boot code source and re-enable access to the primary SPI flash
chip while booted via wdt2 from the alternate chip.
AST2400 datasheet says:
"In the 2nd flash booting mode, all the address mapping to CS0# would be
re-directed to CS1#. And CS0# is not accessible under this mode. To access
CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
register WDT30.bit[1]."
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
drivers/watchdog/aspeed_wdt.c | 65 ++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index cc71861e033a..125dbd349b00 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -53,6 +53,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
#define WDT_CTRL_ENABLE BIT(0)
#define WDT_TIMEOUT_STATUS 0x10
#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
+#define WDT_CLEAR_TIMEOUT_STATUS 0x14
+#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
/*
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
@@ -165,6 +167,60 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd,
return 0;
}
+/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
+static ssize_t access_cs0_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+ u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
+
+ return sprintf(buf, "%u\n",
+ !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
+}
+
+static ssize_t access_cs0_store(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t size)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+ unsigned long val;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+
+ if (val)
+ writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
+ wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
+
+ return size;
+}
+
+/*
+ * This attribute exists only if the system has booted from the alternate
+ * flash with 'alt-boot' option.
+ *
+ * At alternate flash the 'access_cs0' sysfs node provides:
+ * ast2400: a way to get access to the primary SPI flash chip at CS0
+ * after booting from the alternate chip at CS1.
+ * ast2500: a way to restore the normal address mapping from
+ * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
+ *
+ * Clearing the boot code selection and timeout counter also resets to the
+ * initial state the chip select line mapping. When the SoC is in normal
+ * mapping state (i.e. booted from CS0), clearing those bits does nothing for
+ * both versions of the SoC. For alternate boot mode (booted from CS1 due to
+ * wdt2 expiration) the behavior differs as described above.
+ *
+ * This option can be used with wdt2 (watchdog1) only.
+ */
+static DEVICE_ATTR_RW(access_cs0);
+
+static struct attribute *bswitch_attrs[] = {
+ &dev_attr_access_cs0.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(bswitch);
+
static const struct watchdog_ops aspeed_wdt_ops = {
.start = aspeed_wdt_start,
.stop = aspeed_wdt_stop,
@@ -306,9 +362,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
}
status = readl(wdt->base + WDT_TIMEOUT_STATUS);
- if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
+ if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
wdt->wdd.bootstatus = WDIOF_CARDRESET;
+ if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
+ of_device_is_compatible(np, "aspeed,ast2500-wdt"))
+ wdt->wdd.groups = bswitch_groups;
+ }
+
+ dev_set_drvdata(dev, wdt);
+
return devm_watchdog_register_device(dev, &wdt->wdd);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/4] watchdog/aspeed: add support for dual boot
2019-08-28 10:24 ` [PATCH v4 3/4] watchdog/aspeed: add support for dual boot Ivan Mikhaylov
@ 2019-08-31 15:01 ` Guenter Roeck
0 siblings, 0 replies; 7+ messages in thread
From: Guenter Roeck @ 2019-08-31 15:01 UTC (permalink / raw)
To: Ivan Mikhaylov
Cc: Wim Van Sebroeck, Joel Stanley, Andrew Jeffery, linux-watchdog,
linux-arm-kernel, linux-aspeed, linux-kernel, Alexander Amelkin,
openbmc, Rob Herring, Mark Rutland, devicetree
On Wed, Aug 28, 2019 at 01:24:01PM +0300, Ivan Mikhaylov wrote:
> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
> to clear out boot code source and re-enable access to the primary SPI flash
> chip while booted via wdt2 from the alternate chip.
>
> AST2400 datasheet says:
> "In the 2nd flash booting mode, all the address mapping to CS0# would be
> re-directed to CS1#. And CS0# is not accessible under this mode. To access
> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
> register WDT30.bit[1]."
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> drivers/watchdog/aspeed_wdt.c | 65 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index cc71861e033a..125dbd349b00 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -53,6 +53,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> #define WDT_CTRL_ENABLE BIT(0)
> #define WDT_TIMEOUT_STATUS 0x10
> #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> +#define WDT_CLEAR_TIMEOUT_STATUS 0x14
> +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
>
> /*
> * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
> @@ -165,6 +167,60 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd,
> return 0;
> }
>
> +/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
> +static ssize_t access_cs0_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> + u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> +
> + return sprintf(buf, "%u\n",
> + !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
> +}
> +
> +static ssize_t access_cs0_store(struct device *dev,
> + struct device_attribute *attr, const char *buf,
> + size_t size)
> +{
> + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 10, &val))
> + return -EINVAL;
> +
> + if (val)
> + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> +
> + return size;
> +}
> +
> +/*
> + * This attribute exists only if the system has booted from the alternate
> + * flash with 'alt-boot' option.
> + *
> + * At alternate flash the 'access_cs0' sysfs node provides:
> + * ast2400: a way to get access to the primary SPI flash chip at CS0
> + * after booting from the alternate chip at CS1.
> + * ast2500: a way to restore the normal address mapping from
> + * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
> + *
> + * Clearing the boot code selection and timeout counter also resets to the
> + * initial state the chip select line mapping. When the SoC is in normal
> + * mapping state (i.e. booted from CS0), clearing those bits does nothing for
> + * both versions of the SoC. For alternate boot mode (booted from CS1 due to
> + * wdt2 expiration) the behavior differs as described above.
> + *
> + * This option can be used with wdt2 (watchdog1) only.
> + */
> +static DEVICE_ATTR_RW(access_cs0);
> +
> +static struct attribute *bswitch_attrs[] = {
> + &dev_attr_access_cs0.attr,
> + NULL
> +};
> +ATTRIBUTE_GROUPS(bswitch);
> +
> static const struct watchdog_ops aspeed_wdt_ops = {
> .start = aspeed_wdt_start,
> .stop = aspeed_wdt_stop,
> @@ -306,9 +362,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> }
>
> status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
> + if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
> wdt->wdd.bootstatus = WDIOF_CARDRESET;
>
> + if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
> + of_device_is_compatible(np, "aspeed,ast2500-wdt"))
> + wdt->wdd.groups = bswitch_groups;
> + }
> +
> + dev_set_drvdata(dev, wdt);
> +
> return devm_watchdog_register_device(dev, &wdt->wdd);
> }
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot
2019-08-28 10:23 [PATCH v4 0/4] add dual-boot support Ivan Mikhaylov
` (2 preceding siblings ...)
2019-08-28 10:24 ` [PATCH v4 3/4] watchdog/aspeed: add support for dual boot Ivan Mikhaylov
@ 2019-08-28 10:24 ` Ivan Mikhaylov
2019-08-31 15:01 ` Guenter Roeck
3 siblings, 1 reply; 7+ messages in thread
From: Ivan Mikhaylov @ 2019-08-28 10:24 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Joel Stanley, Andrew Jeffery, linux-watchdog, linux-arm-kernel,
linux-aspeed, linux-kernel, Alexander Amelkin, openbmc,
Rob Herring, Mark Rutland, devicetree, Ivan Mikhaylov
The option for the ast2400/2500 to get access to CS0 at runtime.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
.../ABI/testing/sysfs-class-watchdog | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-class-watchdog b/Documentation/ABI/testing/sysfs-class-watchdog
index 6317ade5ad19..675f9b537661 100644
--- a/Documentation/ABI/testing/sysfs-class-watchdog
+++ b/Documentation/ABI/testing/sysfs-class-watchdog
@@ -72,3 +72,37 @@ Description:
It is a read/write file. When read, the currently assigned
pretimeout governor is returned. When written, it sets
the pretimeout governor.
+
+What: /sys/class/watchdog/watchdog1/access_cs0
+Date: August 2019
+Contact: Ivan Mikhaylov <i.mikhaylov@yadro.com>,
+ Alexander Amelkin <a.amelkin@yadro.com>
+Description:
+ It is a read/write file. This attribute exists only if the
+ system has booted from the alternate flash chip due to
+ expiration of a watchdog timer of AST2400/AST2500 when
+ alternate boot function was enabled with 'aspeed,alt-boot'
+ devicetree option for that watchdog or with an appropriate
+ h/w strapping (for WDT2 only).
+
+ At alternate flash the 'access_cs0' sysfs node provides:
+ ast2400: a way to get access to the primary SPI flash
+ chip at CS0 after booting from the alternate
+ chip at CS1.
+ ast2500: a way to restore the normal address mapping
+ from (CS0->CS1, CS1->CS0) to (CS0->CS0,
+ CS1->CS1).
+
+ Clearing the boot code selection and timeout counter also
+ resets to the initial state the chip select line mapping. When
+ the SoC is in normal mapping state (i.e. booted from CS0),
+ clearing those bits does nothing for both versions of the SoC.
+ For alternate boot mode (booted from CS1 due to wdt2
+ expiration) the behavior differs as described above.
+
+ This option can be used with wdt2 (watchdog1) only.
+
+ When read, the current status of the boot code selection is
+ shown. When written with any non-zero value, it clears
+ the boot code selection and the timeout counter, which results
+ in chipselect reset for AST2400/AST2500.
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot
2019-08-28 10:24 ` [PATCH v4 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot Ivan Mikhaylov
@ 2019-08-31 15:01 ` Guenter Roeck
0 siblings, 0 replies; 7+ messages in thread
From: Guenter Roeck @ 2019-08-31 15:01 UTC (permalink / raw)
To: Ivan Mikhaylov
Cc: Wim Van Sebroeck, Joel Stanley, Andrew Jeffery, linux-watchdog,
linux-arm-kernel, linux-aspeed, linux-kernel, Alexander Amelkin,
openbmc, Rob Herring, Mark Rutland, devicetree
On Wed, Aug 28, 2019 at 01:24:02PM +0300, Ivan Mikhaylov wrote:
> The option for the ast2400/2500 to get access to CS0 at runtime.
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-class-watchdog | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-class-watchdog b/Documentation/ABI/testing/sysfs-class-watchdog
> index 6317ade5ad19..675f9b537661 100644
> --- a/Documentation/ABI/testing/sysfs-class-watchdog
> +++ b/Documentation/ABI/testing/sysfs-class-watchdog
> @@ -72,3 +72,37 @@ Description:
> It is a read/write file. When read, the currently assigned
> pretimeout governor is returned. When written, it sets
> the pretimeout governor.
> +
> +What: /sys/class/watchdog/watchdog1/access_cs0
> +Date: August 2019
> +Contact: Ivan Mikhaylov <i.mikhaylov@yadro.com>,
> + Alexander Amelkin <a.amelkin@yadro.com>
> +Description:
> + It is a read/write file. This attribute exists only if the
> + system has booted from the alternate flash chip due to
> + expiration of a watchdog timer of AST2400/AST2500 when
> + alternate boot function was enabled with 'aspeed,alt-boot'
> + devicetree option for that watchdog or with an appropriate
> + h/w strapping (for WDT2 only).
> +
> + At alternate flash the 'access_cs0' sysfs node provides:
> + ast2400: a way to get access to the primary SPI flash
> + chip at CS0 after booting from the alternate
> + chip at CS1.
> + ast2500: a way to restore the normal address mapping
> + from (CS0->CS1, CS1->CS0) to (CS0->CS0,
> + CS1->CS1).
> +
> + Clearing the boot code selection and timeout counter also
> + resets to the initial state the chip select line mapping. When
> + the SoC is in normal mapping state (i.e. booted from CS0),
> + clearing those bits does nothing for both versions of the SoC.
> + For alternate boot mode (booted from CS1 due to wdt2
> + expiration) the behavior differs as described above.
> +
> + This option can be used with wdt2 (watchdog1) only.
> +
> + When read, the current status of the boot code selection is
> + shown. When written with any non-zero value, it clears
> + the boot code selection and the timeout counter, which results
> + in chipselect reset for AST2400/AST2500.
^ permalink raw reply [flat|nested] 7+ messages in thread