From: Andrew Murray <andrew.murray@arm.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, thierry.reding@gmail.com,
jonathanh@nvidia.com, kishon@ti.com,
gustavo.pimentel@synopsys.com, digetx@gmail.com,
mperttunen@nvidia.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins
Date: Mon, 2 Sep 2019 11:18:56 +0100 [thread overview]
Message-ID: <20190902101855.GV14582@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <20190828172850.19871-4-vidyas@nvidia.com>
On Wed, Aug 28, 2019 at 10:58:47PM +0530, Vidya Sagar wrote:
> Add support to configure sideband signal pins when information is present
> in respective controller's device-tree node.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> ---
> V3:
> * Used 'dev' instead of 'pcie->dev'
>
> V2:
> * Addressed review comment from Andrew Murray
> * Handled failure case of pinctrl_pm_select_default_state() cleanly
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index fc0dbeb31d78..77fa6f70bc96 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1304,8 +1304,13 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
> if (ret < 0) {
> dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
> ret);
> - pm_runtime_disable(dev);
> - return ret;
> + goto fail_pm_get_sync;
> + }
> +
> + ret = pinctrl_pm_select_default_state(dev);
> + if (ret < 0) {
> + dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
> + goto fail_pinctrl;
> }
>
> tegra_pcie_init_controller(pcie);
> @@ -1332,7 +1337,9 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>
> fail_host_init:
> tegra_pcie_deinit_controller(pcie);
> +fail_pinctrl:
> pm_runtime_put_sync(dev);
> +fail_pm_get_sync:
> pm_runtime_disable(dev);
> return ret;
> }
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-09-02 10:19 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 17:28 [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-08-28 17:28 ` [PATCH V3 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-09-02 10:40 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 2/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Vidya Sagar
2019-08-29 12:03 ` Thierry Reding
2019-08-29 15:18 ` Vidya Sagar
2019-08-29 16:41 ` Thierry Reding
2019-09-02 10:41 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-09-02 10:18 ` Andrew Murray [this message]
2019-09-02 11:38 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 4/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-09-02 10:29 ` Andrew Murray
2019-09-02 11:40 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 5/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-09-02 10:45 ` Andrew Murray
2019-08-28 17:28 ` [PATCH V3 6/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-09-02 10:47 ` Andrew Murray
2019-09-05 8:14 ` [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 " Vidya Sagar
2019-09-05 9:34 ` Lorenzo Pieralisi
2019-09-05 10:50 ` Vidya Sagar
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