From: Andrew Murray <andrew.murray@arm.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, thierry.reding@gmail.com,
jonathanh@nvidia.com, kishon@ti.com,
gustavo.pimentel@synopsys.com, digetx@gmail.com,
mperttunen@nvidia.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries
Date: Mon, 2 Sep 2019 11:40:10 +0100 [thread overview]
Message-ID: <20190902104009.GB9720@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <20190828172850.19871-2-vidyas@nvidia.com>
On Wed, Aug 28, 2019 at 10:58:45PM +0530, Vidya Sagar wrote:
> Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
> configuration information of a particular PCIe controller.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> ---
> V3:
> * None
>
> V2:
> * None
>
> .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> index 674e5adb2895..0ac1b867ac24 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> @@ -83,6 +83,11 @@ Required properties:
> - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
>
> Optional properties:
> +- pinctrl-names: A list of pinctrl state names.
> + It is mandatory for C5 controller and optional for other controllers.
> + - "default": Configures PCIe I/O for proper operation.
> +- pinctrl-0: phandle for the 'default' state of pin configuration.
> + It is mandatory for C5 controller and optional for other controllers.
> - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
> - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
> improve performance when a platform is designed in such a way that it
> @@ -120,6 +125,9 @@ Tegra194:
> num-lanes = <8>;
> linux,pci-domain = <0>;
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> +
> clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> clock-names = "core";
>
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-09-02 10:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 17:28 [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-08-28 17:28 ` [PATCH V3 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-09-02 10:40 ` Andrew Murray [this message]
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 2/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Vidya Sagar
2019-08-29 12:03 ` Thierry Reding
2019-08-29 15:18 ` Vidya Sagar
2019-08-29 16:41 ` Thierry Reding
2019-09-02 10:41 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-09-02 10:18 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 4/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-09-02 10:29 ` Andrew Murray
2019-09-02 11:40 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 5/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-09-02 10:45 ` Andrew Murray
2019-08-28 17:28 ` [PATCH V3 6/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-09-02 10:47 ` Andrew Murray
2019-09-05 8:14 ` [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 " Vidya Sagar
2019-09-05 9:34 ` Lorenzo Pieralisi
2019-09-05 10:50 ` Vidya Sagar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190902104009.GB9720@e119886-lin.cambridge.arm.com \
--to=andrew.murray@arm.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=kthota@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).