* [PATCH 0/4] New Intel CPU model numbers @ 2019-09-05 19:30 Tony Luck 2019-09-05 19:30 ` [PATCH 1/4] x86/cpu: Add Tiger Lake to Intel family Tony Luck ` (3 more replies) 0 siblings, 4 replies; 5+ messages in thread From: Tony Luck @ 2019-09-05 19:30 UTC (permalink / raw) To: Peter Zijlstra Cc: Tony Luck, Gayatri Kammela, Rahul Tanwar, x86, linux-kernel I'm going to be more aggressive about pushing new CPU model numbers into <asm/intel-family.h>. Basically as soon as Intel talks publicly about some new model and I have the model number, then I'll post the update. Changes to the rest of the kernel will follow at the pace of the various groups that have model specific code ready to be made public. This series has just the model numbers for Tiger Lake and Elkhart Lake. The new Airmont variant also comes with a patch of other spots in the kernel that need updates. Gayatri Kammela (2): x86/cpu: Add Tiger Lake to Intel family x86/cpu: Add Elkhart Lake to Intel family Rahul Tanwar (2): x86/cpu: Add new Airmont variant to Intel family x86/cpu: Update init data for new Airmont CPU model arch/x86/include/asm/intel-family.h | 5 +++++ arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/intel.c | 1 + arch/x86/kernel/tsc_msr.c | 5 +++++ 4 files changed, 12 insertions(+) -- 2.20.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/4] x86/cpu: Add Tiger Lake to Intel family 2019-09-05 19:30 [PATCH 0/4] New Intel CPU model numbers Tony Luck @ 2019-09-05 19:30 ` Tony Luck 2019-09-05 19:30 ` [PATCH 2/4] x86/cpu: Add Elkhart " Tony Luck ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: Tony Luck @ 2019-09-05 19:30 UTC (permalink / raw) To: Peter Zijlstra Cc: Gayatri Kammela, Tony Luck, Rahul Tanwar, x86, linux-kernel From: Gayatri Kammela <gayatri.kammela@intel.com> Add the model numbers/CPUIDs of Tiger Lake mobile and desktop to the Intel family. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Kan Liang <kan.liang@intel.com> Cc: David E. Box <david.e.box@intel.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Suggested-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> --- arch/x86/include/asm/intel-family.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 5c05b2d389c3..7c2ef2e883d5 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -80,6 +80,9 @@ #define INTEL_FAM6_ICELAKE_L 0x7E #define INTEL_FAM6_ICELAKE_NNPI 0x9D +#define INTEL_FAM6_TIGERLAKE_L 0x8C +#define INTEL_FAM6_TIGERLAKE 0x8D + /* "Small Core" Processors (Atom) */ #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] x86/cpu: Add Elkhart Lake to Intel family 2019-09-05 19:30 [PATCH 0/4] New Intel CPU model numbers Tony Luck 2019-09-05 19:30 ` [PATCH 1/4] x86/cpu: Add Tiger Lake to Intel family Tony Luck @ 2019-09-05 19:30 ` Tony Luck 2019-09-05 19:30 ` [PATCH 3/4] x86/cpu: Add new Airmont variant " Tony Luck 2019-09-05 19:30 ` [PATCH 4/4] x86/cpu: Update init data for new Airmont CPU model Tony Luck 3 siblings, 0 replies; 5+ messages in thread From: Tony Luck @ 2019-09-05 19:30 UTC (permalink / raw) To: Peter Zijlstra Cc: Gayatri Kammela, Tony Luck, Rahul Tanwar, x86, linux-kernel From: Gayatri Kammela <gayatri.kammela@intel.com> Add the model number/CPUID of atom based Elkhart Lake to the Intel family. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Kan Liang <kan.liang@intel.com> Cc: David E. Box <david.e.box@intel.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> --- arch/x86/include/asm/intel-family.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 7c2ef2e883d5..55568afe798a 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -106,6 +106,7 @@ #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ #define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */ +#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */ /* Xeon Phi */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] x86/cpu: Add new Airmont variant to Intel family 2019-09-05 19:30 [PATCH 0/4] New Intel CPU model numbers Tony Luck 2019-09-05 19:30 ` [PATCH 1/4] x86/cpu: Add Tiger Lake to Intel family Tony Luck 2019-09-05 19:30 ` [PATCH 2/4] x86/cpu: Add Elkhart " Tony Luck @ 2019-09-05 19:30 ` Tony Luck 2019-09-05 19:30 ` [PATCH 4/4] x86/cpu: Update init data for new Airmont CPU model Tony Luck 3 siblings, 0 replies; 5+ messages in thread From: Tony Luck @ 2019-09-05 19:30 UTC (permalink / raw) To: Peter Zijlstra Cc: Rahul Tanwar, Tony Luck, Gayatri Kammela, x86, linux-kernel From: Rahul Tanwar <rahul.tanwar@linux.intel.com> Add new Airmont variant CPU model to Intel family. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> --- arch/x86/include/asm/intel-family.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 55568afe798a..f04622500da3 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -98,6 +98,7 @@ #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ +#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */ #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ #define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] x86/cpu: Update init data for new Airmont CPU model 2019-09-05 19:30 [PATCH 0/4] New Intel CPU model numbers Tony Luck ` (2 preceding siblings ...) 2019-09-05 19:30 ` [PATCH 3/4] x86/cpu: Add new Airmont variant " Tony Luck @ 2019-09-05 19:30 ` Tony Luck 3 siblings, 0 replies; 5+ messages in thread From: Tony Luck @ 2019-09-05 19:30 UTC (permalink / raw) To: Peter Zijlstra Cc: Rahul Tanwar, Tony Luck, Gayatri Kammela, x86, linux-kernel From: Rahul Tanwar <rahul.tanwar@linux.intel.com> Update properties for newly added Airmont CPU variant. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> --- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/intel.c | 1 + arch/x86/kernel/tsc_msr.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 5cedb679215e..9ae7d1bcd4f4 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL_INTEL(CORE_YONAH, NO_SSB), VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS), + VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS), VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS), VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS), diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e2082ccccf13..c2fdc00df163 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) case INTEL_FAM6_ATOM_SALTWELL_MID: case INTEL_FAM6_ATOM_SALTWELL_TABLET: case INTEL_FAM6_ATOM_SILVERMONT_MID: + case INTEL_FAM6_ATOM_AIRMONT_NP: set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); break; default: diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 067858fe4db8..e0cbe4f2af49 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = { 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }; +static const struct freq_desc freq_desc_lgm = { + 1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 } +}; + static const struct x86_cpu_id tsc_msr_cpu_ids[] = { INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw), INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv), @@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = { INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng), INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht), INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann), + INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm), {} }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-09-05 19:30 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-09-05 19:30 [PATCH 0/4] New Intel CPU model numbers Tony Luck 2019-09-05 19:30 ` [PATCH 1/4] x86/cpu: Add Tiger Lake to Intel family Tony Luck 2019-09-05 19:30 ` [PATCH 2/4] x86/cpu: Add Elkhart " Tony Luck 2019-09-05 19:30 ` [PATCH 3/4] x86/cpu: Add new Airmont variant " Tony Luck 2019-09-05 19:30 ` [PATCH 4/4] x86/cpu: Update init data for new Airmont CPU model Tony Luck
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