From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: jason@lakedaemon.net, andrew@lunn.ch,
gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH 1/3] ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
Date: Fri, 27 Sep 2019 11:28:18 +1200 [thread overview]
Message-ID: <20190926232820.27676-2-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20190926232820.27676-1-chris.packham@alliedtelesis.co.nz>
Enable L2 cache parity and ECC on the db-xc3-24g4xg board so that cache
operations are protected and errors can be flagged to the EDAC
subsystem.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index df048050615f..4ec0ae01b61d 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -33,6 +33,11 @@
};
};
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
&devbus_bootcs {
status = "okay";
--
2.23.0
next prev parent reply other threads:[~2019-09-26 23:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 23:28 [PATCH 0/3] ARM: dts: SDRAM and L2 cache EDAC for Armada SoCs Chris Packham
2019-09-26 23:28 ` Chris Packham [this message]
2019-09-26 23:28 ` [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x Chris Packham
2019-09-26 23:28 ` [PATCH 3/3] ARM: dts: armada-xp: add label to sdram-controller node Chris Packham
2019-10-08 9:57 ` [PATCH 0/3] ARM: dts: SDRAM and L2 cache EDAC for Armada SoCs Gregory CLEMENT
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