From: Julien Grall <julien.grall@arm.com>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: will@kernel.org, catalin.marinas@arm.com, suzuki.poulose@arm.com,
Julien Grall <julien.grall@arm.com>,
mark.brown@arm.com
Subject: [PATCH 1/4] arm64: cpufeature: Effectively expose FRINT capability to userspace
Date: Thu, 3 Oct 2019 12:12:08 +0100 [thread overview]
Message-ID: <20191003111211.483-2-julien.grall@arm.com> (raw)
In-Reply-To: <20191003111211.483-1-julien.grall@arm.com>
The HWCAP framework will detect a new capability based on the sanitized
version of the ID registers.
Sanitization is based on a whitelist, so any field not described will end
up to be zeroed.
At the moment, ID_AA64ISAR1_EL1.FRINTTS is not described in
ftr_id_aa64isar1. This means the field will be zeroed and therefore the
userspace will not be able to see the HWCAP even if the hardware
supports the feature.
This can be fixed by describing the field in ftr_id_aa64isar1.
Fixes: ca9503fc9e98 ("arm64: Expose FRINT capabilities to userspace")
Signed-off-by: Julien Grall <julien.grall@arm.com>
Cc: mark.brown@arm.com
---
arch/arm64/kernel/cpufeature.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9323bcc40a58..cabebf1a7976 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -136,6 +136,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
--
2.11.0
next prev parent reply other threads:[~2019-10-03 11:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 11:12 [PATCH 0/4] arm64/cpufeature: Fix + doc update Julien Grall
2019-10-03 11:12 ` Julien Grall [this message]
2019-10-04 10:36 ` [PATCH 1/4] arm64: cpufeature: Effectively expose FRINT capability to userspace Will Deacon
2019-10-03 11:12 ` [PATCH 2/4] docs/arm64: elf_hwcaps: sort the HWCAP{,2} documentation by ascending value Julien Grall
2019-10-03 11:12 ` [PATCH 3/4] docs/arm64: elf_hwcaps: Document HWCAP_SB Julien Grall
2019-10-03 11:12 ` [PATCH 4/4] docs/arm64: cpu-feature-registers: Documents missing visible fields Julien Grall
2019-10-31 16:48 ` Julien Grall
2019-10-31 17:15 ` Catalin Marinas
2019-10-04 10:37 ` [PATCH 0/4] arm64/cpufeature: Fix + doc update Will Deacon
2019-10-04 16:29 ` Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191003111211.483-2-julien.grall@arm.com \
--to=julien.grall@arm.com \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.brown@arm.com \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).