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From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: [PATCH 4/8] clocksource/drivers/timer-atmel-tcb: rework 32khz clock selection
Date: Thu, 10 Oct 2019 00:40:02 +0200
Message-ID: <20191009224006.5021-5-alexandre.belloni@bootlin.com> (raw)
In-Reply-To: <20191009224006.5021-1-alexandre.belloni@bootlin.com>

On all the supported SoCs, the slow clock is always ATMEL_TC_TIMER_CLOCK5,
avoid looking it up and pass it directly to setup_clkevents.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 drivers/clocksource/timer-atmel-tcb.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 7427b07495a8..b255a4a1a36b 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -346,7 +346,7 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
-static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
+static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
 
 static const struct of_device_id atmel_tcb_of_match[] = {
 	{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
@@ -362,7 +362,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
 	u64 (*tc_sched_clock)(void);
 	u32 rate, divided_rate = 0;
 	int best_divisor_idx = -1;
-	int clk32k_divisor_idx = -1;
 	int bits;
 	int i;
 	int ret;
@@ -416,12 +415,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
 		unsigned divisor = atmel_tcb_divisors[i];
 		unsigned tmp;
 
-		/* remember 32 KiHz clock for later */
-		if (!divisor) {
-			clk32k_divisor_idx = i;
-			continue;
-		}
-
 		tmp = rate / divisor;
 		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 		if (best_divisor_idx > 0) {
@@ -467,7 +460,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
 		goto err_disable_t1;
 
 	/* channel 2:  periodic and oneshot timer support */
-	ret = setup_clkevents(&tc, clk32k_divisor_idx);
+	ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
 	if (ret)
 		goto err_unregister_clksrc;
 
-- 
2.21.0


  parent reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-09 22:39 [PATCH 0/8] clocksource/drivers/timer-atmel-tcb: add sama5d2 support Alexandre Belloni
2019-10-09 22:39 ` [PATCH 1/8] dt-bindings: mfd: atmel-tcb: convert bindings to json-schema Alexandre Belloni
2019-10-15 22:39   ` Rob Herring
2019-10-09 22:40 ` [PATCH 2/8] dt-bindings: mfd: atmel,at91rm9200-tcb: add sama5d2 compatible Alexandre Belloni
2019-10-09 22:40 ` [PATCH 3/8] ARM: dts: at91: sama5d2: add TCB GCLK Alexandre Belloni
2019-10-09 22:40 ` Alexandre Belloni [this message]
2019-10-09 22:40 ` [PATCH 5/8] clocksource/drivers/timer-atmel-tcb: fill tcb_config Alexandre Belloni
2019-10-09 22:40 ` [PATCH 6/8] clocksource/drivers/timer-atmel-tcb: stop using the 32kHz for clockevents Alexandre Belloni
2019-10-09 22:40 ` [PATCH 7/8] clocksource/drivers/timer-atmel-tcb: allow selecting first divider Alexandre Belloni
2019-10-09 22:40 ` [PATCH 8/8] clocksource/drivers/timer-atmel-tcb: add sama5d2 support Alexandre Belloni
2019-10-10  8:26 ` [PATCH 0/8] " Sebastian Andrzej Siewior

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