* [PATCH v2 01/13] dt-bindings: qcom: Add SC7180 bindings
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
` (11 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak, Vinod Koul
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
Also add a new board type 'idp'
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
v2: Added Vinod's Reviewed-by:
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index e39d8f02e33c..0a60ea051541 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -36,6 +36,7 @@ description: |
mdm9615
ipq8074
sdm845
+ sc7180
The 'board' element must be one of the following strings:
@@ -46,6 +47,7 @@ description: |
sbc
hk01
qrd
+ idp
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 01/13] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-22 0:08 ` Matthias Kaehlcke
2019-10-21 6:55 ` [PATCH v2 03/13] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
` (10 subsequent siblings)
12 siblings, 1 reply; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak, Taniya Das
Add skeletal sc7180 SoC dtsi and idp board dts files.
Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2:
* Sorted the nodes in alphabetical order
* Dropped the bi_tcxo/bi_tcxo_ao nodes
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 47 ++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 300 ++++++++++++++++++++++++
3 files changed, 348 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6498a1ec893f..7a5c2f7fe37f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
new file mode 100644
index 000000000000..f8b7e098f5b4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 IDP board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7180.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SC7180 IDP";
+ compatible = "qcom,sc7180-idp";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+
+&qup_uart2_default {
+ pinconf-tx {
+ pins = "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pinconf-rx {
+ pins = "gpio45";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
new file mode 100644
index 000000000000..82bf7cdce6b8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sc7180";
+ reg = <0 0x00100000 0 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ uart2: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_default>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ tlmm: pinctrl@3500000 {
+ compatible = "qcom,sc7180-pinctrl";
+ reg = <0 0x03500000 0 0x300000>,
+ <0 0x03900000 0 0x300000>,
+ <0 0x03d00000 0 0x300000>;
+ reg-names = "west", "north", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 120>;
+
+ qup_uart2_default: qup-uart2-default {
+ pinmux {
+ pins = "gpio44", "gpio45";
+ function = "qup12";
+ };
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic-its@17a40000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0 0x17a40000 0 0x20000>;
+ status = "disabled";
+ };
+ };
+
+ timer@17c20000{
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0 0x17c20000 0 0x1000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c21000 0 0x1000>,
+ <0 0x17c22000 0 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c23000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c25000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c27000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c29000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c2b000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c2d000 0 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
2019-10-21 6:55 ` [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
@ 2019-10-22 0:08 ` Matthias Kaehlcke
2019-10-22 6:15 ` Rajendra Nayak
0 siblings, 1 reply; 19+ messages in thread
From: Matthias Kaehlcke @ 2019-10-22 0:08 UTC (permalink / raw)
To: Rajendra Nayak
Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, Taniya Das
Hi Rajendra,
I don't have all the hardware documentation for a full review, but
find a few comments inline.
On Mon, Oct 21, 2019 at 12:25:11PM +0530, Rajendra Nayak wrote:
> Add skeletal sc7180 SoC dtsi and idp board dts files.
>
> Co-developed-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> v2:
> * Sorted the nodes in alphabetical order
> * Dropped the bi_tcxo/bi_tcxo_ao nodes
>
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 47 ++++
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 300 ++++++++++++++++++++++++
> 3 files changed, 348 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 6498a1ec893f..7a5c2f7fe37f 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> new file mode 100644
> index 000000000000..f8b7e098f5b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * SC7180 IDP board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sc7180.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SC7180 IDP";
> + compatible = "qcom,sc7180-idp";
> +
> + aliases {
> + serial0 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +/* PINCTRL - additions to nodes defined in sc7180.dtsi */
> +
> +&qup_uart2_default {
> + pinconf-tx {
> + pins = "gpio44";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + pinconf-rx {
> + pins = "gpio45";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +};
This config seems reasonable as default for a UART in general.
Would it make sense to configure these in the SoC .dtsi?
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> new file mode 100644
> index 000000000000..82bf7cdce6b8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -0,0 +1,300 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * SC7180 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
Note: depends on "Add Global Clock controller (GCC) driver for SC7180"
(https://patchwork.kernel.org/project/linux-arm-msm/list/?submitter=179717)
which isn't merged yet.
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <38400000>;
> + clock-output-names = "xo_board";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32764>;
> + clock-output-names = "sleep_clk";
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sc7180";
> + reg = <0 0x00100000 0 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + qupv3_id_0: geniqup@ac0000 {
The QUP enumeration is a bit confusing. The Hardware Register
Description has QUPV3_0_QUPV3_ID_0 at 0x00800000 and
QUPV3_1_QUPV3_ID_0 at 0x00a00000. This QUP apparently is
the latter. In the SDM845 DT the QUP @ac0000 has the label
'qupv3_id_1', I guess this should be the same here.
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x00ac0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + uart2: serial@a88000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0 0x00a88000 0 0x4000>;
Related to the comment above: on SDM845 this UART has the label
'uart10'. I understand these are different SoCs, but could you
please clarify the enumeration of the SC7180 QUPs and their ports?
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart2_default>;
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3500000 {
> + compatible = "qcom,sc7180-pinctrl";
> + reg = <0 0x03500000 0 0x300000>,
> + <0 0x03900000 0 0x300000>,
> + <0 0x03d00000 0 0x300000>;
> + reg-names = "west", "north", "south";
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 120>;
> +
> + qup_uart2_default: qup-uart2-default {
> + pinmux {
> + pins = "gpio44", "gpio45";
> + function = "qup12";
> + };
> + };
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic-its@17a40000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + #msi-cells = <1>;
> + reg = <0 0x17a40000 0 0x20000>;
> + status = "disabled";
> + };
> + };
> +
> + timer@17c20000{
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0 0x17c20000 0 0x1000>;
> +
> + frame@17c21000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c21000 0 0x1000>,
> + <0 0x17c22000 0 0x1000>;
> + };
> +
> + frame@17c23000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c23000 0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c25000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c25000 0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c27000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c27000 0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c29000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c29000 0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c2b000 0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0 0x17c2d000 0 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
2019-10-22 0:08 ` Matthias Kaehlcke
@ 2019-10-22 6:15 ` Rajendra Nayak
0 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-22 6:15 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, Taniya Das
Hi Matthias, thanks for the review
On 10/22/2019 5:38 AM, Matthias Kaehlcke wrote:
> Hi Rajendra,
>
> I don't have all the hardware documentation for a full review, but
> find a few comments inline.
>
[]..
>> +#include "sc7180.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SC7180 IDP";
>> + compatible = "qcom,sc7180-idp";
>> +
>> + aliases {
>> + serial0 = &uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&uart2 {
>> + status = "okay";
>> +};
>> +
>> +/* PINCTRL - additions to nodes defined in sc7180.dtsi */
>> +
>> +&qup_uart2_default {
>> + pinconf-tx {
>> + pins = "gpio44";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> +
>> + pinconf-rx {
>> + pins = "gpio45";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +};
>
> This config seems reasonable as default for a UART in general.
> Would it make sense to configure these in the SoC .dtsi?
I think the general rule of thumb that was followed was to have
all pinmux configurations in soc file and all pinconf setting in
the board, even though it meant a bit of duplication in some cases.
See [1] for some discussions around it that happened in the past.
[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1603693.html
>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> new file mode 100644
>> index 000000000000..82bf7cdce6b8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -0,0 +1,300 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * SC7180 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
>
> Note: depends on "Add Global Clock controller (GCC) driver for SC7180"
> (https://patchwork.kernel.org/project/linux-arm-msm/list/?submitter=179717)
> which isn't merged yet.
Right, I did mention it in the cover letter, perhaps I should have mentioned it
as part of this patch as well.
[]..
>> +
>> + soc: soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + gcc: clock-controller@100000 {
>> + compatible = "qcom,gcc-sc7180";
>
>
>
>> + reg = <0 0x00100000 0 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + qupv3_id_0: geniqup@ac0000 {
>
> The QUP enumeration is a bit confusing. The Hardware Register
> Description has QUPV3_0_QUPV3_ID_0 at 0x00800000 and
> QUPV3_1_QUPV3_ID_0 at 0x00a00000. This QUP apparently is
> the latter. In the SDM845 DT the QUP @ac0000 has the label
> 'qupv3_id_1', I guess this should be the same here.
I had a re-look at the documentation again and yes, you are
right, this seems exactly same as on sdm845 except that on
sdm845 the 2 blocks were named QUPV3_0_QUPV3_ID_1 at 0x00800000
and QUPV3_1_QUPV3_ID_1 at 0x00a00000.
I will match this up with the labeling approach we followed on
sdm845. Thanks.
>
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0 0x00ac0000 0 0x6000>;
>> + clock-names = "m-ahb", "s-ahb";
>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + status = "disabled";
>> +
>> + uart2: serial@a88000 {
>> + compatible = "qcom,geni-debug-uart";
>> + reg = <0 0x00a88000 0 0x4000>;
>
> Related to the comment above: on SDM845 this UART has the label
> 'uart10'. I understand these are different SoCs, but could you
> please clarify the enumeration of the SC7180 QUPs and their ports?
I will move this to uart10 once I have the qup instance marked with id_1.
On sdm845 the qup_id_0 had SE instances from 0 to 7 and qup_id_1 had it
from 8 to 15. I will follow the same here so this uart instance would
remain the same as on sdm845, which is uart10.
thanks,
Rajendra
>
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart2_default>;
>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> + };
>> +
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 03/13] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 01/13] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 04/13] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
` (9 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
Joerg Roedel, Mark Rutland
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
v2: No change
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..347869807cf2 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -30,6 +30,7 @@ conditions.
Qcom SoCs implementing "arm,mmu-500" must also include,
as below, SoC-specific compatibles:
"qcom,sdm845-smmu-500", "arm,mmu-500"
+ "qcom,sc7180-smmu-500", "arm,mmu-500"
- reg : Base address and size of the SMMU.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 04/13] arm64: dts: sc7180: Add device node for apps_smmu
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (2 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 03/13] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 05/13] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
` (8 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Vivek Gautam, Rajendra Nayak
From: Vivek Gautam <vivek.gautam@codeaurora.org>
Adding device node for APPS SMMU that is connected to
devices such as display, video, usb, mmc, etc. on SC7180
chipset.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 82bf7cdce6b8..c67d32242ca2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -211,6 +211,94 @@
};
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 05/13] arm64: dts: qcom: sc7180: Add cmd_db reserved area
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (3 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 04/13] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 06/13] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
` (7 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah, Rajendra Nayak
From: Maulik Shah <mkshah@codeaurora.org>
Command_db provides mapping for resource key and address managed
by remote processor. Add cmd_db reserved memory area.
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c67d32242ca2..012ee5028bf6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -32,6 +32,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cmd_db: reserved-memory@80820000 {
+ reg = <0x0 0x80820000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 06/13] arm64: dts: qcom: sc7180: Add rpmh-rsc node
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (4 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 05/13] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 07/13] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
` (6 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah, Rajendra Nayak
From: Maulik Shah <mkshah@codeaurora.org>
Add device bindings for the application processor's rsc. The rsc
contains the TCS that are used for communicating with the hardened
resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 012ee5028bf6..6b3f08133eff 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
@@ -388,6 +389,24 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x18200000 0 0x10000>,
+ <0 0x18210000 0 0x10000>,
+ <0 0x18220000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ };
};
timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 07/13] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (5 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 06/13] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 08/13] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
` (5 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Kiran Gunda, Rajendra Nayak
From: Kiran Gunda <kgunda@codeaurora.org>
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6b3f08133eff..51b8004aa6a7 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -224,6 +224,25 @@
};
};
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0xc440000 0 0x1100>,
+ <0 0xc600000 0 0x2000000>,
+ <0 0xe600000 0 0x100000>,
+ <0 0xe700000 0 0xa0000>,
+ <0 0xc40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 08/13] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (6 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 07/13] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 09/13] arm64: dts: qcom: sc7180-idp: Add RPMh regulators Rajendra Nayak
` (4 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Kiran Gunda, Rajendra Nayak
From: Kiran Gunda <kgunda@codeaurora.org>
Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other
PMIC infra modules.
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2:
* Changed to BSD-3-Clause licence
* Included headers in sc7180-idp.dts
arch/arm64/boot/dts/qcom/pm6150.dtsi | 85 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 47 ++++++++++++++
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 +
3 files changed, 134 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
new file mode 100644
index 000000000000..20eb928e5ce3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
+
+&spmi_bus {
+ pm6150_lsid0: pmic@0 {
+ compatible = "qcom,pm6150", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm6150_pon: pon@800 {
+ compatible = "qcom,pm8998-pon";
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ pm6150_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm6150_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ adc-chan@ADC5_DIE_TEMP {
+ reg = <ADC5_DIE_TEMP>;
+ label = "die_temp";
+ };
+ };
+
+ pm6150_gpio: gpios@c000 {
+ compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
+ reg = <0xc000 0xa00>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+ <0 0xc1 0 IRQ_TYPE_NONE>,
+ <0 0xc2 0 IRQ_TYPE_NONE>,
+ <0 0xc3 0 IRQ_TYPE_NONE>,
+ <0 0xc4 0 IRQ_TYPE_NONE>,
+ <0 0xc5 0 IRQ_TYPE_NONE>,
+ <0 0xc6 0 IRQ_TYPE_NONE>,
+ <0 0xc7 0 IRQ_TYPE_NONE>,
+ <0 0xc8 0 IRQ_TYPE_NONE>,
+ <0 0xc9 0 IRQ_TYPE_NONE>;
+
+ interrupt-names = "pm6150_gpio1", "pm6150_gpio2",
+ "pm6150_gpio3", "pm6150_gpio4",
+ "pm6150_gpio5", "pm6150_gpio6",
+ "pm6150_gpio7", "pm6150_gpio8",
+ "pm6150_gpio9", "pm6150_gpio10";
+ };
+ };
+
+ pm6150_lsid1: pmic@1 {
+ compatible = "qcom,pm6150", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
new file mode 100644
index 000000000000..b17bb1af9367
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm6150l_lsid4: pmic@4 {
+ compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm6150l_gpios: gpios@c000 {
+ compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <4 0xc0 0 IRQ_TYPE_NONE>,
+ <4 0xc1 0 IRQ_TYPE_NONE>,
+ <4 0xc2 0 IRQ_TYPE_NONE>,
+ <4 0xc3 0 IRQ_TYPE_NONE>,
+ <4 0xc4 0 IRQ_TYPE_NONE>,
+ <4 0xc5 0 IRQ_TYPE_NONE>,
+ <4 0xc6 0 IRQ_TYPE_NONE>,
+ <4 0xc7 0 IRQ_TYPE_NONE>,
+ <4 0xc8 0 IRQ_TYPE_NONE>,
+ <4 0xc9 0 IRQ_TYPE_NONE>,
+ <4 0xca 0 IRQ_TYPE_NONE>,
+ <4 0xcb 0 IRQ_TYPE_NONE>;
+
+ interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2",
+ "pm6150l_gpio3", "pm6150l_gpio4",
+ "pm6150l_gpio5", "pm6150l_gpio6",
+ "pm6150l_gpio7", "pm6150l_gpio8",
+ "pm6150l_gpio9", "pm6150l_gpio10",
+ "pm6150l_gpio11", "pm6150l_gpio12";
+ };
+ };
+
+ pm6150l_lsid5: pmic@5 {
+ compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index f8b7e098f5b4..1ba389f1fea9 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -8,6 +8,8 @@
/dts-v1/;
#include "sc7180.dtsi"
+#include "pm6150.dtsi"
+#include "pm6150l.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SC7180 IDP";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 09/13] arm64: dts: qcom: sc7180-idp: Add RPMh regulators
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (7 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 08/13] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 10/13] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
` (3 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Kiran Gunda, Rajendra Nayak
From: Kiran Gunda <kgunda@codeaurora.org>
Add the rpmh regulators for the sc7180 idp platform. This platform
consists of PMIC PM6150 and PM6150l
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: Moved the contents of sc7180-regulators.dtsi into sc7180-idp.dts
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 1ba389f1fea9..505fc50b9f73 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
@@ -24,6 +25,212 @@
};
};
+&apps_rsc {
+ pm6150-rpmh-regulators {
+ compatible = "qcom,pm6150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vreg_s1a_1p1: smps1 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_s4a_1p0: smps4 {
+ regulator-min-microvolt = <824000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s5a_2p0: smps5 {
+ regulator-min-microvolt = <1744000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_l1a_1p2: ldo1 {
+ regulator-min-microvolt = <1178000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2a_1p0: ldo2 {
+ regulator-min-microvolt = <944000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3a_1p0: ldo3 {
+ regulator-min-microvolt = <968000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l4a_0p8: ldo4 {
+ regulator-min-microvolt = <824000>;
+ regulator-max-microvolt = <928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5a_2p7: ldo5 {
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6a_0p6: ldo6 {
+ regulator-min-microvolt = <568000>;
+ regulator-max-microvolt = <648000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9a_0p6: ldo9 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10a_1p8: ldo10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1832000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11a_1p8: ldo11 {
+ regulator-min-microvolt = <1696000>;
+ regulator-max-microvolt = <1904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1696000>;
+ regulator-max-microvolt = <1952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l13a_1p8: ldo13 {
+ regulator-min-microvolt = <1696000>;
+ regulator-max-microvolt = <1904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1728000>;
+ regulator-max-microvolt = <1832000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-min-microvolt = <1696000>;
+ regulator-max-microvolt = <1904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2920000>;
+ regulator-max-microvolt = <3232000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l18a_2p8: ldo18 {
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l19a_2p9: ldo19 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ pm6150l-rpmh-regulators {
+ compatible = "qcom,pm6150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1120000>;
+ regulator-max-microvolt = <1408000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1616000>;
+ regulator-max-microvolt = <1984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1168000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 10/13] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (8 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 09/13] arm64: dts: qcom: sc7180-idp: Add RPMh regulators Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180 Rajendra Nayak
` (2 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Taniya Das, Rajendra Nayak
From: Taniya Das <tdas@codeaurora.org>
Add node for rpmhcc clock driver.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 51b8004aa6a7..b3149a4de5ea 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -175,6 +176,9 @@
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7180";
reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -425,6 +429,13 @@
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sc7180-rpmh-clk";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (9 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 10/13] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-21 8:10 ` Marc Zyngier
2019-10-21 6:55 ` [PATCH v2 12/13] dt-bindings: qcom,pdc: Add compatible " Rajendra Nayak
2019-10-21 6:55 ` [PATCH v2 13/13] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
12 siblings, 1 reply; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah,
Rajendra Nayak, Lina Iyer, Marc Zyngier
From: Maulik Shah <mkshah@codeaurora.org>
Add sc7180 pdc irqchip
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Marc Zyngier <maz@kernel.org>
---
v2: No change
drivers/irqchip/qcom-pdc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index faa7d61b9d6c..954fb599fa9c 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -310,3 +310,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
}
IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
+IRQCHIP_DECLARE(pdc_sc7180, "qcom,sc7180-pdc", qcom_pdc_init);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180
2019-10-21 6:55 ` [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180 Rajendra Nayak
@ 2019-10-21 8:10 ` Marc Zyngier
2019-10-22 5:25 ` Maulik Shah
0 siblings, 1 reply; 19+ messages in thread
From: Marc Zyngier @ 2019-10-21 8:10 UTC (permalink / raw)
To: Rajendra Nayak
Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, Maulik Shah, Lina Iyer
On 2019-10-21 07:55, Rajendra Nayak wrote:
> From: Maulik Shah <mkshah@codeaurora.org>
>
> Add sc7180 pdc irqchip
>
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Lina Iyer <ilina@codeaurora.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
> v2: No change
>
> drivers/irqchip/qcom-pdc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
> index faa7d61b9d6c..954fb599fa9c 100644
> --- a/drivers/irqchip/qcom-pdc.c
> +++ b/drivers/irqchip/qcom-pdc.c
> @@ -310,3 +310,4 @@ static int qcom_pdc_init(struct device_node
> *node, struct device_node *parent)
> }
>
> IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
> +IRQCHIP_DECLARE(pdc_sc7180, "qcom,sc7180-pdc", qcom_pdc_init);
What I gather from these 3 irq-related patches is that as far as
the PDC is concerned, SDM845/850 and SC7180 are strictly identical.
Why the churn?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180
2019-10-21 8:10 ` Marc Zyngier
@ 2019-10-22 5:25 ` Maulik Shah
0 siblings, 0 replies; 19+ messages in thread
From: Maulik Shah @ 2019-10-22 5:25 UTC (permalink / raw)
To: Marc Zyngier, Rajendra Nayak
Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, Lina Iyer
On 10/21/2019 1:40 PM, Marc Zyngier wrote:
> On 2019-10-21 07:55, Rajendra Nayak wrote:
>> From: Maulik Shah <mkshah@codeaurora.org>
>>
>> Add sc7180 pdc irqchip
>>
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Lina Iyer <ilina@codeaurora.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> ---
>> v2: No change
>>
>> drivers/irqchip/qcom-pdc.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
>> index faa7d61b9d6c..954fb599fa9c 100644
>> --- a/drivers/irqchip/qcom-pdc.c
>> +++ b/drivers/irqchip/qcom-pdc.c
>> @@ -310,3 +310,4 @@ static int qcom_pdc_init(struct device_node
>> *node, struct device_node *parent)
>> }
>>
>> IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
>> +IRQCHIP_DECLARE(pdc_sc7180, "qcom,sc7180-pdc", qcom_pdc_init);
>
> What I gather from these 3 irq-related patches is that as far as
> the PDC is concerned, SDM845/850 and SC7180 are strictly identical.
>
> Why the churn?
>
> M.
Hi Marc,
Different compatible were used to distinguish since interrupt mapping
(PDC to GIC) was earlier kept in driver.
Now since mapping is kept in DTSI, we can continue to use
qcom,sdm845-pdc for sc7180.
i will submit another patch to make it more generic for all SoCs like
"qcom,pdc".
Thanks,
Maulik
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 12/13] dt-bindings: qcom,pdc: Add compatible for sc7180
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (10 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 11/13] drivers: irqchip: qcom-pdc: Add irqchip for sc7180 Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
2019-10-25 21:31 ` Rob Herring
2019-10-21 6:55 ` [PATCH v2 13/13] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
12 siblings, 1 reply; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
Lina Iyer, Marc Zyngier
Add the compatible string for sc7180 SoC from Qualcomm.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Marc Zyngier <maz@kernel.org>
---
v2: No change
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
index 8e0797cb1487..f0542b339f40 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -19,6 +19,7 @@ Properties:
Value type: <string>
Definition: Should contain "qcom,<soc>-pdc"
- "qcom,sdm845-pdc": For SDM845
+ - "qcom,sc7180-pdc": For SC7180
- reg:
Usage: required
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 12/13] dt-bindings: qcom,pdc: Add compatible for sc7180
2019-10-21 6:55 ` [PATCH v2 12/13] dt-bindings: qcom,pdc: Add compatible " Rajendra Nayak
@ 2019-10-25 21:31 ` Rob Herring
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2019-10-25 21:31 UTC (permalink / raw)
To: Rajendra Nayak
Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
linux-kernel, Rajendra Nayak, Lina Iyer, Marc Zyngier
On Mon, 21 Oct 2019 12:25:21 +0530, Rajendra Nayak wrote:
> Add the compatible string for sc7180 SoC from Qualcomm.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Lina Iyer <ilina@codeaurora.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
> v2: No change
>
> .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 13/13] arm64: dts: qcom: sc7180: Add pdc interrupt controller
2019-10-21 6:55 [PATCH v2 00/13] Add device tree support for sc7180 Rajendra Nayak
` (11 preceding siblings ...)
2019-10-21 6:55 ` [PATCH v2 12/13] dt-bindings: qcom,pdc: Add compatible " Rajendra Nayak
@ 2019-10-21 6:55 ` Rajendra Nayak
12 siblings, 0 replies; 19+ messages in thread
From: Rajendra Nayak @ 2019-10-21 6:55 UTC (permalink / raw)
To: agross, robh+dt, bjorn.andersson
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah,
Rajendra Nayak, Lina Iyer, Marc Zyngier
From: Maulik Shah <mkshah@codeaurora.org>
Add pdc interrupt controller for sc7180
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Marc Zyngier <maz@kernel.org>
---
v2: No change
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index b3149a4de5ea..31b11dbcd1d4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -184,6 +184,16 @@
#power-domain-cells = <1>;
};
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sc7180-pdc";
+ reg = <0 0xb220000 0 0x30000>;
+ qcom,pdc-ranges = <0 480 15>, <17 497 98>,
+ <119 634 4>, <124 639 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
qupv3_id_0: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x6000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 19+ messages in thread