[PATCH 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support

[PATCH 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support

[Roger Quadros]

Hi,

On J721e platform, the 2 lanes of SERDES PHY are used to achieve
USB Type-C plug flip support without any additional MUX component
by using a lane swap feature.

However, the driver needs to know the Type-C plug orientation before
it can decide whether to swap the lanes or not. This is achieved via a
GPIO named DIR.

Another constraint is that the lane swap must happen only when the PHY
is in inactive state. This is achieved by sampling the GPIO and
programming the lane swap before bringing the PHY out of reset.

This series adds support to read the GPIO and accordingly program
the Lane swap for Type-C plug flip support.

Series must be applied on top of
https://lkml.org/lkml/2019/10/16/517

cheers,
-roger

Roger Quadros (3):
  phy: cadence: Sierra: add phy_reset hook
  dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
  phy: ti: j721e-wiz: Manage typec-gpio-dir

 .../bindings/phy/ti,phy-j721e-wiz.txt         |  9 ++++
 drivers/phy/cadence/phy-cadence-sierra.c      | 10 +++++
 drivers/phy/ti/phy-j721e-wiz.c                | 41 +++++++++++++++++++
 3 files changed, 60 insertions(+)

-- 
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[PATCH 1/3] phy: cadence: Sierra: add phy_reset hook

[Roger Quadros]

This is required if type C driver needs to hold
global reset on J7ES to perform LN10 swap.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index affede8c4368..e6d27bdec22a 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy)
 	return reset_control_assert(ins->lnk_rst);
 }
 
+static int cdns_sierra_phy_reset(struct phy *gphy)
+{
+	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
+
+	reset_control_assert(sp->phy_rst);
+	reset_control_deassert(sp->phy_rst);
+	return 0;
+};
+
 static const struct phy_ops ops = {
 	.init		= cdns_sierra_phy_init,
 	.power_on	= cdns_sierra_phy_on,
 	.power_off	= cdns_sierra_phy_off,
+	.reset		= cdns_sierra_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
-- 
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Re: [PATCH 1/3] phy: cadence: Sierra: add phy_reset hook

[Kishon Vijay Abraham I]

Roger,

On 22/10/19 6:52 PM, Roger Quadros wrote:
> This is required if type C driver needs to hold
> global reset on J7ES to perform LN10 swap.

Can you replace "This" with something more specific.

Thanks
Kishon
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
> index affede8c4368..e6d27bdec22a 100644
> --- a/drivers/phy/cadence/phy-cadence-sierra.c
> +++ b/drivers/phy/cadence/phy-cadence-sierra.c
> @@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy)
>  	return reset_control_assert(ins->lnk_rst);
>  }
>  
> +static int cdns_sierra_phy_reset(struct phy *gphy)
> +{
> +	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
> +
> +	reset_control_assert(sp->phy_rst);
> +	reset_control_deassert(sp->phy_rst);
> +	return 0;
> +};
> +
>  static const struct phy_ops ops = {
>  	.init		= cdns_sierra_phy_init,
>  	.power_on	= cdns_sierra_phy_on,
>  	.power_off	= cdns_sierra_phy_off,
> +	.reset		= cdns_sierra_phy_reset,
>  	.owner		= THIS_MODULE,
>  };
>  
> 

Re: [PATCH 1/3] phy: cadence: Sierra: add phy_reset hook

[Roger Quadros]

Kishon,

On 23/10/2019 10:36, Kishon Vijay Abraham I wrote:
> Roger,
> 
> On 22/10/19 6:52 PM, Roger Quadros wrote:
>> This is required if type C driver needs to hold
>> global reset on J7ES to perform LN10 swap.
> 
> Can you replace "This" with something more specific.

I meant this patch, but I will revise the commit message.

cheers,
-roger
> 
> Thanks
> Kishon
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> ---
>>   drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
>> index affede8c4368..e6d27bdec22a 100644
>> --- a/drivers/phy/cadence/phy-cadence-sierra.c
>> +++ b/drivers/phy/cadence/phy-cadence-sierra.c
>> @@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy)
>>   	return reset_control_assert(ins->lnk_rst);
>>   }
>>   
>> +static int cdns_sierra_phy_reset(struct phy *gphy)
>> +{
>> +	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
>> +
>> +	reset_control_assert(sp->phy_rst);
>> +	reset_control_deassert(sp->phy_rst);
>> +	return 0;
>> +};
>> +
>>   static const struct phy_ops ops = {
>>   	.init		= cdns_sierra_phy_init,
>>   	.power_on	= cdns_sierra_phy_on,
>>   	.power_off	= cdns_sierra_phy_off,
>> +	.reset		= cdns_sierra_phy_reset,
>>   	.owner		= THIS_MODULE,
>>   };
>>   
>>

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[PATCH 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO

[Roger Quadros]

This is an optional GPIO, if specified will be used to
swap lane 0 and lane 1 based on GPIO status. This is required
to achieve plug flip support for USB Type-C.

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Allow the DT node to specify the time (in ms) that we need
to wait before sampling the DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 .../devicetree/bindings/phy/ti,phy-j721e-wiz.txt         | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
index 19b4c3e855d6..253535a8819f 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
@@ -24,6 +24,15 @@ Optional properties:
 assigned-clocks and assigned-clock-parents: As documented in the generic
 clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt
 
+ - typec-dir-gpios: GPIO to signal Type-C cable orientation for lane swap.
+     If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
+     achieve the funtionality of an exernal type-C plug flip mux.
+
+ - typec-dir-debounce: Number of milliseconds to wait before sampling
+     typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
+     Type-C spec states minimum CC pin debounce of 100 ms and maximum
+     of 200 ms.
+
 Required subnodes:
  - Clock Subnode: WIZ node should have '3' subnodes for each of the clock
      selects it supports. The clock subnodes should have the following names
-- 
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[PATCH 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir

[Roger Quadros]

Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/phy/ti/phy-j721e-wiz.c | 41 ++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2a95da843e9f..2becdbcb762a 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -9,6 +9,8 @@
 #include <dt-bindings/phy/phy.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/mux/consumer.h>
@@ -22,6 +24,7 @@
 #define WIZ_SERDES_CTRL		0x404
 #define WIZ_SERDES_TOP_CTRL	0x408
 #define WIZ_SERDES_RST		0x40c
+#define WIZ_SERDES_TYPEC	0x410
 #define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
 
 #define WIZ_MAX_LANES		4
@@ -29,6 +32,8 @@
 #define WIZ_DIV_NUM_CLOCKS_16G	2
 #define WIZ_DIV_NUM_CLOCKS_10G	1
 
+#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
+
 enum wiz_lane_standard_mode {
 	LANE_MODE_GEN1,
 	LANE_MODE_GEN2,
@@ -206,6 +211,8 @@ struct wiz {
 	u32			num_lanes;
 	struct platform_device	*serdes_pdev;
 	struct reset_controller_dev wiz_phy_reset_dev;
+	struct gpio_desc	*gpio_typec_dir;
+	int			typec_dir_delay;
 };
 
 static int wiz_reset(struct wiz *wiz)
@@ -703,6 +710,21 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
 	struct wiz *wiz = dev_get_drvdata(dev);
 	int ret;
 
+	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
+	if (id == 0 && wiz->gpio_typec_dir) {
+		if (wiz->typec_dir_delay)
+			msleep_interruptible(wiz->typec_dir_delay);
+
+		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) {
+			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+					   WIZ_SERDES_TYPEC_LN10_SWAP,
+					   WIZ_SERDES_TYPEC_LN10_SWAP);
+		} else {
+			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+					   WIZ_SERDES_TYPEC_LN10_SWAP, 0);
+		}
+	}
+
 	if (id == 0) {
 		ret = regmap_field_write(wiz->phy_reset_n, true);
 		return ret;
@@ -789,6 +811,25 @@ static int wiz_probe(struct platform_device *pdev)
 		goto err_addr_to_resource;
 	}
 
+	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
+						      GPIOD_IN);
+	if (IS_ERR(wiz->gpio_typec_dir)) {
+		ret = PTR_ERR(wiz->gpio_typec_dir);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to request typec-dir gpio: %d\n",
+				ret);
+		goto err_addr_to_resource;
+	}
+
+	if (wiz->gpio_typec_dir) {
+		ret = of_property_read_u32(node, "typec-dir-debounce",
+					   &wiz->typec_dir_delay);
+		if (ret && ret != -EINVAL) {
+			dev_err(dev, "Invalid typec-dir-debounce property\n");
+			goto err_addr_to_resource;
+		}
+	}
+
 	wiz->dev = dev;
 	wiz->regmap = regmap;
 	wiz->num_lanes = num_lanes;
-- 
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Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir

[Jyri Sarha]

On 22/10/2019 16:22, Roger Quadros wrote:
> Based on this GPIO state we need to configure LN10
> bit to swap lane0 and lane1 if required (flipped connector).
> 
> Type-C companions typically need some time after the cable is
> plugged before and before they reflect the correct status of
> Type-C plug orientation on the DIR line.
> 
> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
> of 100 ms (min) to 200 ms (max).
> 
> Use the DT property to figure out if we need to add delay
> or not before sampling the Type-C DIR line.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  drivers/phy/ti/phy-j721e-wiz.c | 41 ++++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index 2a95da843e9f..2becdbcb762a 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -9,6 +9,8 @@
>  #include <dt-bindings/phy/phy.h>
>  #include <linux/clk.h>
>  #include <linux/clk-provider.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/mux/consumer.h>
> @@ -22,6 +24,7 @@
>  #define WIZ_SERDES_CTRL		0x404
>  #define WIZ_SERDES_TOP_CTRL	0x408
>  #define WIZ_SERDES_RST		0x40c
> +#define WIZ_SERDES_TYPEC	0x410
>  #define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
>  
>  #define WIZ_MAX_LANES		4
> @@ -29,6 +32,8 @@
>  #define WIZ_DIV_NUM_CLOCKS_16G	2
>  #define WIZ_DIV_NUM_CLOCKS_10G	1
>  
> +#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
> +
>  enum wiz_lane_standard_mode {
>  	LANE_MODE_GEN1,
>  	LANE_MODE_GEN2,
> @@ -206,6 +211,8 @@ struct wiz {
>  	u32			num_lanes;
>  	struct platform_device	*serdes_pdev;
>  	struct reset_controller_dev wiz_phy_reset_dev;
> +	struct gpio_desc	*gpio_typec_dir;
> +	int			typec_dir_delay;
>  };
>  
>  static int wiz_reset(struct wiz *wiz)
> @@ -703,6 +710,21 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
>  	struct wiz *wiz = dev_get_drvdata(dev);
>  	int ret;
>  
> +	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
> +	if (id == 0 && wiz->gpio_typec_dir) {
> +		if (wiz->typec_dir_delay)
> +			msleep_interruptible(wiz->typec_dir_delay);
> +
> +		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) {
> +			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
> +					   WIZ_SERDES_TYPEC_LN10_SWAP,
> +					   WIZ_SERDES_TYPEC_LN10_SWAP);

A nit pick, but wouldn't it be more coherent with the rest of the driver
to define a REG_FIELD also for TYPEC_LN10_SWAP bit?

> +		} else {
> +			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
> +					   WIZ_SERDES_TYPEC_LN10_SWAP, 0);
> +		}
> +	}
> +
>  	if (id == 0) {
>  		ret = regmap_field_write(wiz->phy_reset_n, true);
>  		return ret;
> @@ -789,6 +811,25 @@ static int wiz_probe(struct platform_device *pdev)
>  		goto err_addr_to_resource;
>  	}
>  
> +	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
> +						      GPIOD_IN);
> +	if (IS_ERR(wiz->gpio_typec_dir)) {
> +		ret = PTR_ERR(wiz->gpio_typec_dir);
> +		if (ret != -EPROBE_DEFER)
> +			dev_err(dev, "Failed to request typec-dir gpio: %d\n",
> +				ret);
> +		goto err_addr_to_resource;
> +	}
> +
> +	if (wiz->gpio_typec_dir) {
> +		ret = of_property_read_u32(node, "typec-dir-debounce",
> +					   &wiz->typec_dir_delay);
> +		if (ret && ret != -EINVAL) {
> +			dev_err(dev, "Invalid typec-dir-debounce property\n");
> +			goto err_addr_to_resource;
> +		}
> +	}
> +
>  	wiz->dev = dev;
>  	wiz->regmap = regmap;
>  	wiz->num_lanes = num_lanes;
> 


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Re: [PATCH 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir

[Roger Quadros]

On 23/10/2019 08:28, Jyri Sarha wrote:
> On 22/10/2019 16:22, Roger Quadros wrote:
>> Based on this GPIO state we need to configure LN10
>> bit to swap lane0 and lane1 if required (flipped connector).
>>
>> Type-C companions typically need some time after the cable is
>> plugged before and before they reflect the correct status of
>> Type-C plug orientation on the DIR line.
>>
>> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
>> of 100 ms (min) to 200 ms (max).
>>
>> Use the DT property to figure out if we need to add delay
>> or not before sampling the Type-C DIR line.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> ---
>>   drivers/phy/ti/phy-j721e-wiz.c | 41 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
>> index 2a95da843e9f..2becdbcb762a 100644
>> --- a/drivers/phy/ti/phy-j721e-wiz.c
>> +++ b/drivers/phy/ti/phy-j721e-wiz.c
>> @@ -9,6 +9,8 @@
>>   #include <dt-bindings/phy/phy.h>
>>   #include <linux/clk.h>
>>   #include <linux/clk-provider.h>
>> +#include <linux/gpio.h>
>> +#include <linux/gpio/consumer.h>
>>   #include <linux/io.h>
>>   #include <linux/module.h>
>>   #include <linux/mux/consumer.h>
>> @@ -22,6 +24,7 @@
>>   #define WIZ_SERDES_CTRL		0x404
>>   #define WIZ_SERDES_TOP_CTRL	0x408
>>   #define WIZ_SERDES_RST		0x40c
>> +#define WIZ_SERDES_TYPEC	0x410
>>   #define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
>>   
>>   #define WIZ_MAX_LANES		4
>> @@ -29,6 +32,8 @@
>>   #define WIZ_DIV_NUM_CLOCKS_16G	2
>>   #define WIZ_DIV_NUM_CLOCKS_10G	1
>>   
>> +#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
>> +
>>   enum wiz_lane_standard_mode {
>>   	LANE_MODE_GEN1,
>>   	LANE_MODE_GEN2,
>> @@ -206,6 +211,8 @@ struct wiz {
>>   	u32			num_lanes;
>>   	struct platform_device	*serdes_pdev;
>>   	struct reset_controller_dev wiz_phy_reset_dev;
>> +	struct gpio_desc	*gpio_typec_dir;
>> +	int			typec_dir_delay;
>>   };
>>   
>>   static int wiz_reset(struct wiz *wiz)
>> @@ -703,6 +710,21 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
>>   	struct wiz *wiz = dev_get_drvdata(dev);
>>   	int ret;
>>   
>> +	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
>> +	if (id == 0 && wiz->gpio_typec_dir) {
>> +		if (wiz->typec_dir_delay)
>> +			msleep_interruptible(wiz->typec_dir_delay);
>> +
>> +		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) {
>> +			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
>> +					   WIZ_SERDES_TYPEC_LN10_SWAP,
>> +					   WIZ_SERDES_TYPEC_LN10_SWAP);
> 
> A nit pick, but wouldn't it be more coherent with the rest of the driver
> to define a REG_FIELD also for TYPEC_LN10_SWAP bit?

I agree. Although, I hate fields as you need to do so much boilerplate just to
flip one bit.

cheers,
-roger
> 
>> +		} else {
>> +			regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
>> +					   WIZ_SERDES_TYPEC_LN10_SWAP, 0);
>> +		}
>> +	}
>> +
>>   	if (id == 0) {
>>   		ret = regmap_field_write(wiz->phy_reset_n, true);
>>   		return ret;
>> @@ -789,6 +811,25 @@ static int wiz_probe(struct platform_device *pdev)
>>   		goto err_addr_to_resource;
>>   	}
>>   
>> +	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
>> +						      GPIOD_IN);
>> +	if (IS_ERR(wiz->gpio_typec_dir)) {
>> +		ret = PTR_ERR(wiz->gpio_typec_dir);
>> +		if (ret != -EPROBE_DEFER)
>> +			dev_err(dev, "Failed to request typec-dir gpio: %d\n",
>> +				ret);
>> +		goto err_addr_to_resource;
>> +	}
>> +
>> +	if (wiz->gpio_typec_dir) {
>> +		ret = of_property_read_u32(node, "typec-dir-debounce",
>> +					   &wiz->typec_dir_delay);
>> +		if (ret && ret != -EINVAL) {
>> +			dev_err(dev, "Invalid typec-dir-debounce property\n");
>> +			goto err_addr_to_resource;
>> +		}
>> +	}
>> +
>>   	wiz->dev = dev;
>>   	wiz->regmap = regmap;
>>   	wiz->num_lanes = num_lanes;
>>
> 
> 

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