[PATCH v3 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support

[PATCH v3 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support

[Roger Quadros]

Hi,

On J721e platform, the 2 lanes of SERDES PHY are used to achieve
USB Type-C plug flip support without any additional MUX component
by using a lane swap feature.

However, the driver needs to know the Type-C plug orientation before
it can decide whether to swap the lanes or not. This is achieved via a
GPIO named DIR.

Another constraint is that the lane swap must happen only when the PHY
is in inactive state. This is achieved by sampling the GPIO and
programming the lane swap before bringing the PHY out of reset.

This series adds support to read the GPIO and accordingly program
the Lane swap for Type-C plug flip support.

Series must be applied on top of
https://lkml.org/lkml/2019/10/23/589

cheers,
-roger

Changelog:
v3
- Rebase on v2 of PHY series and update DT binding to yaml

v2
- revise commit log of patch 1
- use regmap_field in patch 3

Roger Quadros (3):
  phy: cadence: Sierra: add phy_reset hook
  dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
  phy: ti: j721e-wiz: Manage typec-gpio-dir

 .../bindings/phy/ti,phy-j721e-wiz.yaml        | 15 ++++++
 drivers/phy/cadence/phy-cadence-sierra.c      | 10 ++++
 drivers/phy/ti/phy-j721e-wiz.c                | 48 +++++++++++++++++++
 3 files changed, 73 insertions(+)

-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v3 1/3] phy: cadence: Sierra: add phy_reset hook

[Roger Quadros]

Some platforms e.g. J721e need lane swap register
to be programmed before reset is deasserted.
This patch ensures that we propagate the phy_reset
back to the reset controller driver.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 04c28cbb6d39..7fed61211716 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy)
 	return reset_control_assert(ins->lnk_rst);
 }
 
+static int cdns_sierra_phy_reset(struct phy *gphy)
+{
+	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
+
+	reset_control_assert(sp->phy_rst);
+	reset_control_deassert(sp->phy_rst);
+	return 0;
+};
+
 static const struct phy_ops ops = {
 	.init		= cdns_sierra_phy_init,
 	.power_on	= cdns_sierra_phy_on,
 	.power_off	= cdns_sierra_phy_off,
+	.reset		= cdns_sierra_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v3 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO

[Roger Quadros]

This is an optional GPIO, if specified will be used to
swap lane 0 and lane 1 based on GPIO status. This is required
to achieve plug flip support for USB Type-C.

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Allow the DT node to specify the time (in ms) that we need
to wait before sampling the DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 8a1eccee6c1d..5dab0010bcdf 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -53,6 +53,21 @@ properties:
   assigned-clock-parents:
     maxItems: 2
 
+  typec-dir-gpios:
+    maxItems: 1
+    description:
+      GPIO to signal Type-C cable orientation for lane swap.
+      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
+      achieve the funtionality of an exernal type-C plug flip mux.
+
+  typec-dir-debounce:
+    $ref: '/schemas/types.yaml#/definitions/uint32'
+    description:
+      Number of milliseconds to wait before sampling
+      typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
+      Type-C spec states minimum CC pin debounce of 100 ms and maximum
+      of 200 ms.
+
 patternProperties:
   "^pll[0|1]_refclk$":
     type: object
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v3 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir

[Roger Quadros]

Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/phy/ti/phy-j721e-wiz.c | 48 ++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2a95da843e9f..02b949406b7b 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -9,6 +9,8 @@
 #include <dt-bindings/phy/phy.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/mux/consumer.h>
@@ -22,6 +24,7 @@
 #define WIZ_SERDES_CTRL		0x404
 #define WIZ_SERDES_TOP_CTRL	0x408
 #define WIZ_SERDES_RST		0x40c
+#define WIZ_SERDES_TYPEC	0x410
 #define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
 
 #define WIZ_MAX_LANES		4
@@ -29,6 +32,8 @@
 #define WIZ_DIV_NUM_CLOCKS_16G	2
 #define WIZ_DIV_NUM_CLOCKS_10G	1
 
+#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
+
 enum wiz_lane_standard_mode {
 	LANE_MODE_GEN1,
 	LANE_MODE_GEN2,
@@ -94,6 +99,9 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
 	REG_FIELD(WIZ_LANECTL(3), 24, 25),
 };
 
+static const struct reg_field typec_ln10_swap =
+					REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
+
 struct wiz_clk_mux {
 	struct clk_hw		hw;
 	struct regmap_field	*field;
@@ -201,11 +209,14 @@ struct wiz {
 	struct regmap_field	*pma_cmn_refclk_mode;
 	struct regmap_field	*pma_cmn_refclk_dig_div;
 	struct regmap_field	*pma_cmn_refclk1_dig_div;
+	struct regmap_field	*typec_ln10_swap;
 
 	struct device		*dev;
 	u32			num_lanes;
 	struct platform_device	*serdes_pdev;
 	struct reset_controller_dev wiz_phy_reset_dev;
+	struct gpio_desc	*gpio_typec_dir;
+	int			typec_dir_delay;
 };
 
 static int wiz_reset(struct wiz *wiz)
@@ -404,6 +415,13 @@ static int wiz_regfield_init(struct wiz *wiz)
 		}
 	}
 
+	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
+						       typec_ln10_swap);
+	if (IS_ERR(wiz->typec_ln10_swap)) {
+		dev_err(dev, "LN10_SWAP reg field init failed\n");
+		return PTR_ERR(wiz->typec_ln10_swap);
+	}
+
 	return 0;
 }
 
@@ -703,6 +721,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
 	struct wiz *wiz = dev_get_drvdata(dev);
 	int ret;
 
+	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
+	if (id == 0 && wiz->gpio_typec_dir) {
+		if (wiz->typec_dir_delay)
+			msleep_interruptible(wiz->typec_dir_delay);
+
+		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
+			regmap_field_write(wiz->typec_ln10_swap, 1);
+		else
+			regmap_field_write(wiz->typec_ln10_swap, 0);
+	}
+
 	if (id == 0) {
 		ret = regmap_field_write(wiz->phy_reset_n, true);
 		return ret;
@@ -789,6 +818,25 @@ static int wiz_probe(struct platform_device *pdev)
 		goto err_addr_to_resource;
 	}
 
+	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
+						      GPIOD_IN);
+	if (IS_ERR(wiz->gpio_typec_dir)) {
+		ret = PTR_ERR(wiz->gpio_typec_dir);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to request typec-dir gpio: %d\n",
+				ret);
+		goto err_addr_to_resource;
+	}
+
+	if (wiz->gpio_typec_dir) {
+		ret = of_property_read_u32(node, "typec-dir-debounce",
+					   &wiz->typec_dir_delay);
+		if (ret && ret != -EINVAL) {
+			dev_err(dev, "Invalid typec-dir-debounce property\n");
+			goto err_addr_to_resource;
+		}
+	}
+
 	wiz->dev = dev;
 	wiz->regmap = regmap;
 	wiz->num_lanes = num_lanes;
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO

[Rob Herring]

On Thu, Oct 24, 2019 at 02:40:41PM +0300, Roger Quadros wrote:
> This is an optional GPIO, if specified will be used to
> swap lane 0 and lane 1 based on GPIO status. This is required
> to achieve plug flip support for USB Type-C.
> 
> Type-C companions typically need some time after the cable is
> plugged before and before they reflect the correct status of
> Type-C plug orientation on the DIR line.
> 
> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
> of 100 ms (min) to 200 ms (max).
> 
> Allow the DT node to specify the time (in ms) that we need
> to wait before sampling the DIR line.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Cc: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> index 8a1eccee6c1d..5dab0010bcdf 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> @@ -53,6 +53,21 @@ properties:
>    assigned-clock-parents:
>      maxItems: 2
>  
> +  typec-dir-gpios:

TI specific or could be generic?

> +    maxItems: 1
> +    description:
> +      GPIO to signal Type-C cable orientation for lane swap.
> +      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
> +      achieve the funtionality of an exernal type-C plug flip mux.

s/exernal/external/

> +
> +  typec-dir-debounce:

Needs '-ms' suffix.

> +    $ref: '/schemas/types.yaml#/definitions/uint32'

then you can drop this because standard units have type already.

> +    description:
> +      Number of milliseconds to wait before sampling
> +      typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
> +      Type-C spec states minimum CC pin debounce of 100 ms and maximum
> +      of 200 ms.

Express this as constraints:

minimum: 100
maximum: 200
default: ???

If the spec minimum is 100ms, then doesn't sampling ASAP violate the 
spec?

> +
>  patternProperties:
>    "^pll[0|1]_refclk$":
>      type: object
> -- 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 

Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO

[Roger Quadros]

Hi Rob,

On 25/10/2019 23:06, Rob Herring wrote:
> On Thu, Oct 24, 2019 at 02:40:41PM +0300, Roger Quadros wrote:
>> This is an optional GPIO, if specified will be used to
>> swap lane 0 and lane 1 based on GPIO status. This is required
>> to achieve plug flip support for USB Type-C.
>>
>> Type-C companions typically need some time after the cable is
>> plugged before and before they reflect the correct status of
>> Type-C plug orientation on the DIR line.
>>
>> Type-C Spec specifies CC attachment debounce time (tCCDebounce)
>> of 100 ms (min) to 200 ms (max).
>>
>> Allow the DT node to specify the time (in ms) that we need
>> to wait before sampling the DIR line.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> Cc: Rob Herring <robh@kernel.org>
>> ---
>>   .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>> index 8a1eccee6c1d..5dab0010bcdf 100644
>> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>> @@ -53,6 +53,21 @@ properties:
>>     assigned-clock-parents:
>>       maxItems: 2
>>   
>> +  typec-dir-gpios:
> 
> TI specific or could be generic?

This driver is TI only.

> 
>> +    maxItems: 1
>> +    description:
>> +      GPIO to signal Type-C cable orientation for lane swap.
>> +      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
>> +      achieve the funtionality of an exernal type-C plug flip mux.
> 
> s/exernal/external/
> 
>> +
>> +  typec-dir-debounce:
> 
> Needs '-ms' suffix.
> 
>> +    $ref: '/schemas/types.yaml#/definitions/uint32'
> 
> then you can drop this because standard units have type already.
> 
>> +    description:
>> +      Number of milliseconds to wait before sampling
>> +      typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
>> +      Type-C spec states minimum CC pin debounce of 100 ms and maximum
>> +      of 200 ms.
> 
> Express this as constraints:
> 
> minimum: 100
> maximum: 200
> default: ???
> 
> If the spec minimum is 100ms, then doesn't sampling ASAP violate the
> spec?

Good point. I'll change the default to 100.

Some board solutions seem to take even longer than 200. I can set
1000 ms as maximum.

> 
>> +
>>   patternProperties:
>>     "^pll[0|1]_refclk$":
>>       type: object
>> -- 
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>

--
cheers,
-roger
  
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki