* [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver
@ 2019-10-24 20:27 Chris Packham
2019-10-24 20:27 ` [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc Chris Packham
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Chris Packham @ 2019-10-24 20:27 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, mark.rutland, rjui,
sbranden, bcm-kernel-feedback-list
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Chris Packham
This is ported this from Broadcom's XLDK (now heavily modified). There seem to
be 3 different IP blocks for 3 separate banks of GPIOs in the iProc chips.
I've dropped everything except support for the Chip Common A GPIO
controller because the other blocks actually seem to be supportable with
other drivers. The driver itself is halfway between pinctrl-nsp-gpio.c
and pinctrl-iproc-gpio.c.
Chris Packham (2):
dt-bindings: gpio: brcm: Add bindings for xgs-iproc
gpio: Add xgs-iproc driver
.../bindings/gpio/brcm,xgs-iproc-gpio.yaml | 70 ++++
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-xgs-iproc.c | 321 ++++++++++++++++++
4 files changed, 401 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml
create mode 100644 drivers/gpio/gpio-xgs-iproc.c
--
2.23.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc 2019-10-24 20:27 [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Chris Packham @ 2019-10-24 20:27 ` Chris Packham 2019-10-25 17:12 ` Rob Herring 2019-10-24 20:27 ` [PATCH v4 2/2] gpio: Add xgs-iproc driver Chris Packham 2019-10-24 20:36 ` [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Scott Branden 2 siblings, 1 reply; 8+ messages in thread From: Chris Packham @ 2019-10-24 20:27 UTC (permalink / raw) To: linus.walleij, bgolaszewski, robh+dt, mark.rutland, rjui, sbranden, bcm-kernel-feedback-list Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Chris Packham This GPIO controller is present on a number of Broadcom switch ASICs with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio blocks but different enough to require a separate driver. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Notes: Changes in v4: - rename brcm,xgs-iproc.yaml -> brcm,xgs-iproc-gpio.yaml as suggested Changes in v3: - incorporate review comments from Rob and Bart Changes in v2: - Document as DT schema - Include ngpios, #gpio-cells and gpio-controller properties .../bindings/gpio/brcm,xgs-iproc-gpio.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml new file mode 100644 index 000000000000..ec1fd3a64aa2 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom XGS iProc GPIO controller + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +description: | + This controller is the Chip Common A GPIO present on a number of Broadcom + switch ASICs with integrated SoCs. + +properties: + compatible: + const: brcm,iproc-gpio-cca + + reg: + items: + - description: the I/O address containing the GPIO controller + registers. + - description: the I/O address containing the Chip Common A interrupt + registers. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + minimum: 0 + maximum: 32 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +dependencies: + interrupt-controller: [ interrupts ] + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpio@18000060 { + compatible = "brcm,iproc-gpio-cca"; + #gpio-cells = <2>; + reg = <0x18000060 0x50>, + <0x18000000 0x50>; + ngpios = <12>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + }; + + +... -- 2.23.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc 2019-10-24 20:27 ` [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc Chris Packham @ 2019-10-25 17:12 ` Rob Herring 2019-10-28 20:02 ` Chris Packham 0 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2019-10-25 17:12 UTC (permalink / raw) To: Chris Packham Cc: Linus Walleij, Bartosz Golaszewski, Mark Rutland, Ray Jui, Scott Branden, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, open list:GPIO SUBSYSTEM, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-kernel On Thu, Oct 24, 2019 at 3:27 PM Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > > This GPIO controller is present on a number of Broadcom switch ASICs > with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio > blocks but different enough to require a separate driver. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > > Notes: > Changes in v4: > - rename brcm,xgs-iproc.yaml -> brcm,xgs-iproc-gpio.yaml as suggested > > Changes in v3: > - incorporate review comments from Rob and Bart > > Changes in v2: > - Document as DT schema > - Include ngpios, #gpio-cells and gpio-controller properties > > .../bindings/gpio/brcm,xgs-iproc-gpio.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > new file mode 100644 > index 000000000000..ec1fd3a64aa2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc.yaml# Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml: $id: path/filename 'gpio/brcm,xgs-iproc.yaml' doesn't match actual filename Otherwise, Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc 2019-10-25 17:12 ` Rob Herring @ 2019-10-28 20:02 ` Chris Packham 0 siblings, 0 replies; 8+ messages in thread From: Chris Packham @ 2019-10-28 20:02 UTC (permalink / raw) To: robh+dt Cc: linux-kernel, bcm-kernel-feedback-list, devicetree, linus.walleij, linux-gpio, rjui, mark.rutland, sbranden, bgolaszewski, linux-arm-kernel Hi Rob, On Fri, 2019-10-25 at 12:12 -0500, Rob Herring wrote: > On Thu, Oct 24, 2019 at 3:27 PM Chris Packham > <chris.packham@alliedtelesis.co.nz> wrote: > > > > This GPIO controller is present on a number of Broadcom switch ASICs > > with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio > > blocks but different enough to require a separate driver. > > > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > > --- > > > > Notes: > > Changes in v4: > > - rename brcm,xgs-iproc.yaml -> brcm,xgs-iproc-gpio.yaml as suggested > > > > Changes in v3: > > - incorporate review comments from Rob and Bart > > > > Changes in v2: > > - Document as DT schema > > - Include ngpios, #gpio-cells and gpio-controller properties > > > > .../bindings/gpio/brcm,xgs-iproc-gpio.yaml | 70 +++++++++++++++++++ > > 1 file changed, 70 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > > > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > > new file mode 100644 > > index 000000000000..ec1fd3a64aa2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > > @@ -0,0 +1,70 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc.yaml# > > Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml: $id: > path/filename 'gpio/brcm,xgs-iproc.yaml' doesn't match actual filename > > Otherwise, > > Reviewed-by: Rob Herring <robh@kernel.org> I'll send a quick v5 of just this patch with the minor correction and your reviewed-by. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] gpio: Add xgs-iproc driver 2019-10-24 20:27 [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Chris Packham 2019-10-24 20:27 ` [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc Chris Packham @ 2019-10-24 20:27 ` Chris Packham 2019-10-29 14:58 ` Linus Walleij 2019-11-07 10:32 ` Jon Hunter 2019-10-24 20:36 ` [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Scott Branden 2 siblings, 2 replies; 8+ messages in thread From: Chris Packham @ 2019-10-24 20:27 UTC (permalink / raw) To: linus.walleij, bgolaszewski, robh+dt, mark.rutland, rjui, sbranden, bcm-kernel-feedback-list Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Chris Packham This driver supports the Chip Common A GPIO controller present on a number of Broadcom switch ASICs with integrated SoCs. The controller is similar to the pinctrl-nsp-gpio and pinctrl-iproc-gpio blocks but different enough that a separate driver is required. This has been ported from Broadcom's XLDK 5.0.3 retaining only the CCA support (pinctrl-iproc-gpio covers CCB). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Notes: Changes in v4: - rename the config option to GPIO_BCM_XGS_IPROC and place alphabetically - sort #includes alphabetically Changes in v3: - prefix local #defines with 'IPROC' - use {readl,writel}_relaxed - remove unnecessary headers - actually use spinlock to guard hardware accesses Changes in v2: - use more of the generic infrastructure for gpio chips - handling the root interrupt is still done manually due to sharing with uart0. drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-xgs-iproc.c | 321 ++++++++++++++++++++++++++++++++++ 3 files changed, 331 insertions(+) create mode 100644 drivers/gpio/gpio-xgs-iproc.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 38e096e6925f..04396787fbb0 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -147,6 +147,15 @@ config GPIO_BCM_KONA help Turn on GPIO support for Broadcom "Kona" chips. +config GPIO_BCM_XGS_IPROC + tristate "BRCM XGS iProc GPIO support" + depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + default ARCH_BCM_IPROC + help + Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. + config GPIO_BRCMSTB tristate "BRCMSTB GPIO support" default y if (ARCH_BRCMSTB || BMIPS_GENERIC) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d2fd19c15bae..8725d158a964 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o +obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o diff --git a/drivers/gpio/gpio-xgs-iproc.c b/drivers/gpio/gpio-xgs-iproc.c new file mode 100644 index 000000000000..a3fdd95cc9e6 --- /dev/null +++ b/drivers/gpio/gpio-xgs-iproc.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Broadcom + */ + +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#define IPROC_CCA_INT_F_GPIOINT BIT(0) +#define IPROC_CCA_INT_STS 0x20 +#define IPROC_CCA_INT_MASK 0x24 + +#define IPROC_GPIO_CCA_DIN 0x0 +#define IPROC_GPIO_CCA_DOUT 0x4 +#define IPROC_GPIO_CCA_OUT_EN 0x8 +#define IPROC_GPIO_CCA_INT_LEVEL 0x10 +#define IPROC_GPIO_CCA_INT_LEVEL_MASK 0x14 +#define IPROC_GPIO_CCA_INT_EVENT 0x18 +#define IPROC_GPIO_CCA_INT_EVENT_MASK 0x1C +#define IPROC_GPIO_CCA_INT_EDGE 0x24 + +struct iproc_gpio_chip { + struct irq_chip irqchip; + struct gpio_chip gc; + spinlock_t lock; + struct device *dev; + void __iomem *base; + void __iomem *intr; +}; + +static inline struct iproc_gpio_chip * +to_iproc_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct iproc_gpio_chip, gc); +} + +static void iproc_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 irq_type, event_status = 0; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_status |= BIT(pin); + writel_relaxed(event_status, + chip->base + IPROC_GPIO_CCA_INT_EVENT); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void iproc_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 int_mask, irq_type, event_mask; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_mask |= 1 << pin; + writel_relaxed(event_mask, + chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + } else { + int_mask |= 1 << pin; + writel_relaxed(int_mask, + chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void iproc_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 irq_type, int_mask, event_mask; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_mask &= ~BIT(pin); + writel_relaxed(event_mask, + chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + } else { + int_mask &= ~BIT(pin); + writel_relaxed(int_mask, + chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 event_pol, int_pol; + int ret = 0; + + spin_lock_irqsave(&chip->lock, flags); + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); + event_pol &= ~BIT(pin); + writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); + break; + case IRQ_TYPE_EDGE_FALLING: + event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); + event_pol |= BIT(pin); + writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); + break; + case IRQ_TYPE_LEVEL_HIGH: + int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + int_pol &= ~BIT(pin); + writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); + break; + case IRQ_TYPE_LEVEL_LOW: + int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + int_pol |= BIT(pin); + writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); + break; + default: + /* should not come here */ + ret = -EINVAL; + goto out_unlock; + } + + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq); + else if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq); + +out_unlock: + spin_unlock_irqrestore(&chip->lock, flags); + + return ret; +} + +static irqreturn_t iproc_gpio_irq_handler(int irq, void *data) +{ + struct gpio_chip *gc = (struct gpio_chip *)data; + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int bit; + unsigned long int_bits = 0; + u32 int_status; + + /* go through the entire GPIOs and handle all interrupts */ + int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS); + if (int_status & IPROC_CCA_INT_F_GPIOINT) { + u32 event, level; + + /* Get level and edge interrupts */ + event = + readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT); + level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN); + level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + level &= + readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + int_bits = level | event; + + for_each_set_bit(bit, &int_bits, gc->ngpio) + generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit)); + } + + return int_bits ? IRQ_HANDLED : IRQ_NONE; +} + +static int iproc_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *dn = pdev->dev.of_node; + struct iproc_gpio_chip *chip; + u32 num_gpios; + int irq, ret; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + platform_set_drvdata(pdev, chip); + spin_lock_init(&chip->lock); + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + ret = bgpio_init(&chip->gc, dev, 4, + chip->base + IPROC_GPIO_CCA_DIN, + chip->base + IPROC_GPIO_CCA_DOUT, + NULL, + chip->base + IPROC_GPIO_CCA_OUT_EN, + NULL, + 0); + if (ret) { + dev_err(dev, "unable to init GPIO chip\n"); + return ret; + } + + chip->gc.label = dev_name(dev); + if (of_property_read_u32(dn, "ngpios", &num_gpios)) + chip->gc.ngpio = num_gpios; + + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + struct gpio_irq_chip *girq; + struct irq_chip *irqc; + u32 val; + + irqc = &chip->irqchip; + irqc->name = dev_name(dev); + irqc->irq_ack = iproc_gpio_irq_ack; + irqc->irq_mask = iproc_gpio_irq_mask; + irqc->irq_unmask = iproc_gpio_irq_unmask; + irqc->irq_set_type = iproc_gpio_irq_set_type; + + chip->intr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->intr)) + return PTR_ERR(chip->intr); + + /* Enable GPIO interrupts for CCA GPIO */ + val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); + val |= IPROC_CCA_INT_F_GPIOINT; + writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); + + /* + * Directly request the irq here instead of passing + * a flow-handler to gpiochip_set_chained_irqchip, + * because the irq is shared. + */ + ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler, + IRQF_SHARED, chip->gc.label, &chip->gc); + if (ret) { + dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret); + return ret; + } + + girq = &chip->gc.irq; + girq->chip = irqc; + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } + + ret = devm_gpiochip_add_data(dev, &chip->gc, chip); + if (ret) { + dev_err(dev, "unable to add GPIO chip\n"); + return ret; + } + + return 0; +} + +static int __exit iproc_gpio_remove(struct platform_device *pdev) +{ + struct iproc_gpio_chip *chip; + + chip = platform_get_drvdata(pdev); + if (!chip) + return -ENODEV; + + if (chip->intr) { + u32 val; + + val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); + val &= ~IPROC_CCA_INT_F_GPIOINT; + writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); + } + + return 0; +} + +static const struct of_device_id bcm_iproc_gpio_of_match[] __initconst = { + { .compatible = "brcm,iproc-gpio-cca" }, + {} +}; +MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match); + +static struct platform_driver bcm_iproc_gpio_driver = { + .driver = { + .name = "iproc-xgs-gpio", + .owner = THIS_MODULE, + .of_match_table = bcm_iproc_gpio_of_match, + }, + .probe = iproc_gpio_probe, + .remove = iproc_gpio_remove, +}; + +module_platform_driver(bcm_iproc_gpio_driver); + +MODULE_DESCRIPTION("XGS IPROC GPIO driver"); +MODULE_LICENSE("GPL v2"); -- 2.23.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] gpio: Add xgs-iproc driver 2019-10-24 20:27 ` [PATCH v4 2/2] gpio: Add xgs-iproc driver Chris Packham @ 2019-10-29 14:58 ` Linus Walleij 2019-11-07 10:32 ` Jon Hunter 1 sibling, 0 replies; 8+ messages in thread From: Linus Walleij @ 2019-10-29 14:58 UTC (permalink / raw) To: Chris Packham Cc: Bartosz Golaszewski, Rob Herring, Mark Rutland, Ray Jui, Scott Branden, bcm-kernel-feedback-list, open list:GPIO SUBSYSTEM, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, linux-kernel On Thu, Oct 24, 2019 at 10:27 PM Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > This driver supports the Chip Common A GPIO controller present on a > number of Broadcom switch ASICs with integrated SoCs. The controller is > similar to the pinctrl-nsp-gpio and pinctrl-iproc-gpio blocks but > different enough that a separate driver is required. > > This has been ported from Broadcom's XLDK 5.0.3 retaining only the CCA > support (pinctrl-iproc-gpio covers CCB). > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > > Notes: > Changes in v4: > - rename the config option to GPIO_BCM_XGS_IPROC and place alphabetically > - sort #includes alphabetically Patch applied, great work on this patch, it's very lean and clean now! Got a minor thing I wanna look at, will send a patch on top if I find it useful. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] gpio: Add xgs-iproc driver 2019-10-24 20:27 ` [PATCH v4 2/2] gpio: Add xgs-iproc driver Chris Packham 2019-10-29 14:58 ` Linus Walleij @ 2019-11-07 10:32 ` Jon Hunter 1 sibling, 0 replies; 8+ messages in thread From: Jon Hunter @ 2019-11-07 10:32 UTC (permalink / raw) To: Chris Packham, linus.walleij, bgolaszewski, robh+dt, mark.rutland, rjui, sbranden, bcm-kernel-feedback-list Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, linux-tegra On 24/10/2019 21:27, Chris Packham wrote: > This driver supports the Chip Common A GPIO controller present on a > number of Broadcom switch ASICs with integrated SoCs. The controller is > similar to the pinctrl-nsp-gpio and pinctrl-iproc-gpio blocks but > different enough that a separate driver is required. > > This has been ported from Broadcom's XLDK 5.0.3 retaining only the CCA > support (pinctrl-iproc-gpio covers CCB). > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > > Notes: > Changes in v4: > - rename the config option to GPIO_BCM_XGS_IPROC and place alphabetically > - sort #includes alphabetically > > Changes in v3: > - prefix local #defines with 'IPROC' > - use {readl,writel}_relaxed > - remove unnecessary headers > - actually use spinlock to guard hardware accesses > > Changes in v2: > - use more of the generic infrastructure for gpio chips > - handling the root interrupt is still done manually due to sharing with uart0. > > drivers/gpio/Kconfig | 9 + > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-xgs-iproc.c | 321 ++++++++++++++++++++++++++++++++++ > 3 files changed, 331 insertions(+) > create mode 100644 drivers/gpio/gpio-xgs-iproc.c > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 38e096e6925f..04396787fbb0 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -147,6 +147,15 @@ config GPIO_BCM_KONA > help > Turn on GPIO support for Broadcom "Kona" chips. > > +config GPIO_BCM_XGS_IPROC > + tristate "BRCM XGS iProc GPIO support" > + depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) > + select GPIO_GENERIC > + select GPIOLIB_IRQCHIP > + default ARCH_BCM_IPROC > + help > + Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. > + > config GPIO_BRCMSTB > tristate "BRCMSTB GPIO support" > default y if (ARCH_BRCMSTB || BMIPS_GENERIC) > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index d2fd19c15bae..8725d158a964 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -34,6 +34,7 @@ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o > obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o > obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o > obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o > +obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o > obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o > obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o > obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o > diff --git a/drivers/gpio/gpio-xgs-iproc.c b/drivers/gpio/gpio-xgs-iproc.c > new file mode 100644 > index 000000000000..a3fdd95cc9e6 > --- /dev/null > +++ b/drivers/gpio/gpio-xgs-iproc.c ... > +static const struct of_device_id bcm_iproc_gpio_of_match[] __initconst = { > + { .compatible = "brcm,iproc-gpio-cca" }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match); This patch is generating the following warning when built as a module ... MODPOST vmlinux.o WARNING: vmlinux.o(.data+0x834d0): Section mismatch in reference from the variable bcm_iproc_gpio_driver to the variable .init.rodata:bcm_iproc_gpio_of_match The variable bcm_iproc_gpio_driver references the variable __initconst bcm_iproc_gpio_of_match If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console This then leads to the following crash on boot ... [ 13.586799] ------------[ cut here ]------------ [ 13.591406] Ignoring spurious kernel translation fault at virtual address ffff80001139a990 [ 13.599659] WARNING: CPU: 0 PID: 5 at /home/jonathanh/workdir/tegra/mlt-linux_next/kernel/arch/arm64/mm/fault.c:302 __do_kernel_fault+0xd0/0x128 [ 13.612582] Modules linked in: ina3221(+) ip_tables x_tables ipv6 nf_defrag_ipv6 [ 13.619966] CPU: 0 PID: 5 Comm: kworker/0:0 Tainted: G S 5.4.0-rc1-00031-g6a41b6c5fc20 #11 [ 13.629509] Hardware name: NVIDIA Jetson TX2 Developer Kit (DT) [ 13.635416] Workqueue: events deferred_probe_work_func [ 13.640540] pstate: 40000085 (nZcv daIf -PAN -UAO) [ 13.645318] pc : __do_kernel_fault+0xd0/0x128 [ 13.649663] lr : __do_kernel_fault+0xd0/0x128 [ 13.654006] sp : ffff800010073a10 [ 13.657308] x29: ffff800010073a10 x28: ffff0001f5ccb700 [ 13.662605] x27: ffff0001f7185730 x26: ffff8000117aff28 [ 13.667901] x25: 0000000000000000 x24: 0000000000000025 [ 13.673198] x23: 0000000060000085 x22: ffff80001139a990 [ 13.678495] x21: ffff800010073a80 x20: 0000000000000025 [ 13.683792] x19: 0000000096000007 x18: ffffffffffffffff [ 13.689089] x17: 0000000000000000 x16: 0000000000000000 [ 13.694386] x15: ffff8000117998c8 x14: 3131303030386666 [ 13.699681] x13: 6666207373657264 x12: 6461206c61757472 [ 13.704978] x11: 697620746120746c x10: 756166206e6f6974 [ 13.710274] x9 : 616c736e61727420 x8 : 6c656e72656b2073 [ 13.715570] x7 : 0000000000000160 x6 : ffff0001f717c180 [ 13.720867] x5 : 0000000000000001 x4 : ffff0001f717c180 [ 13.726162] x3 : 0000000000000006 x2 : 0000000000000007 [ 13.731458] x1 : aa4a2528bb290a00 x0 : 0000000000000000 [ 13.736756] Call trace: [ 13.739194] __do_kernel_fault+0xd0/0x128 [ 13.743192] do_translation_fault+0x40/0x70 [ 13.747363] do_mem_abort+0x3c/0x98 [ 13.750839] el1_da+0x20/0x94 [ 13.753799] __of_match_node+0x40/0x88 [ 13.757535] of_match_node+0x3c/0x60 [ 13.761099] of_match_device+0x18/0x28 [ 13.764837] platform_match+0x4c/0xd0 [ 13.768488] __device_attach_driver+0x34/0xc0 [ 13.772832] bus_for_each_drv+0x70/0xc8 [ 13.776655] __device_attach+0xdc/0x140 [ 13.780479] device_initial_probe+0x10/0x18 [ 13.784649] bus_probe_device+0x94/0xa0 [ 13.788471] deferred_probe_work_func+0x6c/0xa0 [ 13.792990] process_one_work+0x1c8/0x358 [ 13.796986] worker_thread+0x48/0x460 [ 13.800637] kthread+0xf0/0x120 [ 13.803767] ret_from_fork+0x10/0x1c [ 13.807331] ---[ end trace ce728f2656bbae67 ]--- I think we need to drop the __initconst from the match table. I will send a patch. Cheers Jon -- nvpublic ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver 2019-10-24 20:27 [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Chris Packham 2019-10-24 20:27 ` [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc Chris Packham 2019-10-24 20:27 ` [PATCH v4 2/2] gpio: Add xgs-iproc driver Chris Packham @ 2019-10-24 20:36 ` Scott Branden 2 siblings, 0 replies; 8+ messages in thread From: Scott Branden @ 2019-10-24 20:36 UTC (permalink / raw) To: Chris Packham, linus.walleij, bgolaszewski, robh+dt, mark.rutland, rjui, sbranden, bcm-kernel-feedback-list Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel Patch Series looks ok. On 2019-10-24 1:27 p.m., Chris Packham wrote: > This is ported this from Broadcom's XLDK (now heavily modified). There seem to > be 3 different IP blocks for 3 separate banks of GPIOs in the iProc chips. > > I've dropped everything except support for the Chip Common A GPIO > controller because the other blocks actually seem to be supportable with > other drivers. The driver itself is halfway between pinctrl-nsp-gpio.c > and pinctrl-iproc-gpio.c. > > Chris Packham (2): > dt-bindings: gpio: brcm: Add bindings for xgs-iproc > gpio: Add xgs-iproc driver Acked-by: Scott Branden <scott.branden@broadcom.com> > > .../bindings/gpio/brcm,xgs-iproc-gpio.yaml | 70 ++++ > drivers/gpio/Kconfig | 9 + > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-xgs-iproc.c | 321 ++++++++++++++++++ > 4 files changed, 401 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml > create mode 100644 drivers/gpio/gpio-xgs-iproc.c > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-11-07 10:32 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-24 20:27 [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Chris Packham 2019-10-24 20:27 ` [PATCH v4 1/2] dt-bindings: gpio: brcm: Add bindings for xgs-iproc Chris Packham 2019-10-25 17:12 ` Rob Herring 2019-10-28 20:02 ` Chris Packham 2019-10-24 20:27 ` [PATCH v4 2/2] gpio: Add xgs-iproc driver Chris Packham 2019-10-29 14:58 ` Linus Walleij 2019-11-07 10:32 ` Jon Hunter 2019-10-24 20:36 ` [PATCH v4 0/2] gpio: brcm: XGS iProc GPIO driver Scott Branden
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