From: Andrew Murray <andrew.murray@arm.com>
To: Dilip Kota <eswara.kota@linux.intel.com>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lorenzo.pieralisi@arm.com, robh@kernel.org,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
hch@infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com,
cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com
Subject: Re: [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link
Date: Fri, 25 Oct 2019 10:34:57 +0100 [thread overview]
Message-ID: <20191025093457.GY47056@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <6a209452-f569-4f6a-8aea-5c9f84167f5a@linux.intel.com>
On Tue, Oct 22, 2019 at 05:20:00PM +0800, Dilip Kota wrote:
> Hi Andrew Murray,
>
> On 10/21/2019 9:38 PM, Andrew Murray wrote:
> > On Mon, Oct 21, 2019 at 02:39:20PM +0800, Dilip Kota wrote:
> > > PCIe RC driver on Intel Gateway SoCs have a requirement
> > > of changing link width and speed on the fly.
> > > So add the sysfs attributes to show and store the link
> > > properties.
> > > Add the respective link resize function in pcie DesignWare
> > > framework so that Intel PCIe driver can use during link
> > > width configuration on the fly.
> > >
> > > Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
> > > +/*
> > > + * Link width change on the fly is not always successful.
> > > + * It also depends on the partner.
> > > + */
> > > +static ssize_t pcie_width_store(struct device *dev,
> > > + struct device_attribute *attr,
> > > + const char *buf, size_t len)
> > > +{
> > > + struct intel_pcie_port *lpp = dev_get_drvdata(dev);
> > > + unsigned long val;
> > > + int ret;
> > > +
> > > + lpp = dev_get_drvdata(dev);
> > > +
> > > + ret = kstrtoul(buf, 10, &val);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + if (val > lpp->max_width)
> > > + return -EINVAL;
> > > +
> > > + /* HW auto bandwidth negotiation must be enabled */
> > > + pcie_rc_cfg_wr_mask(lpp, PCI_EXP_LNKCTL_HAWD, 0,
> > > + PCIE_CAP_OFST + PCI_EXP_LNKCTL);
> > > + dw_pcie_link_width_resize(&lpp->pci, val);
> > > +
> > > + return len;
> > > +}
> > > +static DEVICE_ATTR_WO(pcie_width);
> > > +
> > > +static struct attribute *pcie_cfg_attrs[] = {
> > > + &dev_attr_pcie_link_status.attr,
> > > + &dev_attr_pcie_speed.attr,
> > > + &dev_attr_pcie_width.attr,
> > > + NULL,
> > > +};
> > Is there a reason that these are limited only to the Intel driver and
> > not the wider set of DWC drivers?
> >
> > Is there anything specific here about the Intel GW driver?
>
> Yes, they need intel_pcie_max_speed_setup() and pcie_link_gen_to_str().
> Once intel_pcie_max_speed_setup() moved to DesignWare framework (as per
> Bjorn Helgaas inputs) and use pcie_link_speed[] array instead of
> pcie_link_gen_to_str() (as per gustavo pimentel inputs) we can move this to
> PCIe DesignWare framework or to pci sysfs file.
I think the key concern here is this: If you introduce sysfs controls that
represent generic PCI concepts (such as changing the link speed) - the concept
isn't limited to a particular host controller, it's limited to PCI. Therefore
the sysfs control should also apply more widely to all PCI controllers. This
is important as otherwise you may end up getting a slightly different user
interface to achieve the same consequence depending on the host-controller in
use.
If each controller driver has a different way of doing things, then it lends
itself to having some set of ops that they can all implement. Or perhaps there
is a middle-ground solution where this applies just to DWC devices and not all
devices.
Thanks,
Andrew Murray
>
> Regards,
> Dilip
>
> >
> > Thanks,
> >
> > Andrew Murray
> >
> > > +ATTRIBUTE_GROUPS(pcie_cfg);
> > > +
> > > +static int intel_pcie_sysfs_init(struct intel_pcie_port *lpp)
> > > +{
> > > + return devm_device_add_groups(lpp->pci.dev, pcie_cfg_groups);
> > > +}
> > > +
> > > static void __intel_pcie_remove(struct intel_pcie_port *lpp)
> > > {
> > > intel_pcie_core_irq_disable(lpp);
> > > @@ -490,8 +591,17 @@ static int intel_pcie_rc_init(struct pcie_port *pp)
> > > {
> > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev);
> > > + int ret;
> > > - return intel_pcie_host_setup(lpp);
> > > + ret = intel_pcie_host_setup(lpp);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = intel_pcie_sysfs_init(lpp);
> > > + if (ret)
> > > + __intel_pcie_remove(lpp);
> > > +
> > > + return ret;
> > > }
> > > int intel_pcie_msi_init(struct pcie_port *pp)
> > > --
> > > 2.11.0
> > >
next prev parent reply other threads:[~2019-10-25 9:35 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-21 6:39 [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-10-21 6:39 ` [PATCH v4 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-10-21 11:19 ` Andrew Murray
2019-10-22 10:15 ` Dilip Kota
2019-10-24 20:31 ` Martin Blumenstingl
2019-10-29 7:53 ` Dilip Kota
2019-10-25 16:53 ` Rob Herring
2019-10-29 8:34 ` Dilip Kota
2019-10-31 10:51 ` Dilip Kota
2019-10-31 18:35 ` Rob Herring
2019-10-21 6:39 ` [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-10-21 8:29 ` Gustavo Pimentel
2019-10-21 10:44 ` Dilip Kota
2019-10-22 10:18 ` Dilip Kota
2019-10-22 11:44 ` andriy.shevchenko
2019-10-25 9:01 ` Andrew Murray
2019-10-29 6:14 ` Dilip Kota
2019-10-21 13:03 ` Andrew Murray
2019-10-22 9:04 ` Dilip Kota
2019-10-25 9:09 ` Andrew Murray
2019-10-29 8:59 ` Dilip Kota
2019-11-01 10:59 ` Andrew Murray
2019-11-04 9:34 ` Dilip Kota
2019-11-04 10:47 ` Andrew Murray
2019-10-21 17:17 ` Bjorn Helgaas
2019-10-22 9:07 ` Dilip Kota
2019-10-22 13:09 ` Bjorn Helgaas
2019-10-29 7:45 ` Dilip Kota
2019-10-24 6:57 ` kbuild test robot
2019-10-25 13:11 ` kbuild test robot
2019-10-25 13:11 ` [RFC PATCH] dwc: PCI: intel: intel_pcie_msi_init() can be static kbuild test robot
2019-10-21 6:39 ` [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link Dilip Kota
2019-10-21 8:40 ` Gustavo Pimentel
2019-10-21 10:34 ` Dilip Kota
2019-10-21 13:38 ` Andrew Murray
2019-10-21 17:18 ` Bjorn Helgaas
2019-10-22 9:27 ` Dilip Kota
2019-10-22 12:59 ` Bjorn Helgaas
2019-10-29 9:31 ` Dilip Kota
2019-10-30 22:14 ` Bjorn Helgaas
2019-10-30 23:31 ` Rafael J. Wysocki
2019-10-31 2:56 ` Bjorn Helgaas
2019-10-31 9:13 ` Rafael J. Wysocki
2019-10-31 13:01 ` Bjorn Helgaas
2019-10-31 10:47 ` Dilip Kota
2019-10-31 13:22 ` Bjorn Helgaas
2019-11-01 5:47 ` Dilip Kota
2019-11-01 11:30 ` Andrew Murray
2019-10-29 10:42 ` Rafael J. Wysocki
2019-10-29 12:36 ` Bjorn Helgaas
2019-10-22 9:20 ` Dilip Kota
2019-10-25 9:34 ` Andrew Murray [this message]
2019-10-29 9:51 ` Dilip Kota
2019-10-21 8:08 ` [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Gustavo Pimentel
2019-10-21 8:31 ` Dilip Kota
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