From: Dilip Kota <eswara.kota@linux.intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lorenzo.pieralisi@arm.com, andrew.murray@arm.com,
robh@kernel.org, martin.blumenstingl@googlemail.com,
linux-pci@vger.kernel.org, hch@infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
andriy.shevchenko@intel.com, cheol.yong.kim@intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver
Date: Tue, 29 Oct 2019 15:45:56 +0800 [thread overview]
Message-ID: <f74cdada-c58b-7238-9be1-8b001ca1fb84@linux.intel.com> (raw)
In-Reply-To: <20191022130905.GA133961@google.com>
On 10/22/2019 9:09 PM, Bjorn Helgaas wrote:
> On Tue, Oct 22, 2019 at 05:07:47PM +0800, Dilip Kota wrote:
>> On 10/22/2019 1:17 AM, Bjorn Helgaas wrote:
>>> On Mon, Oct 21, 2019 at 02:39:19PM +0800, Dilip Kota wrote:
>>>> Add support to PCIe RC controller on Intel Gateway SoCs.
>>>> PCIe controller is based of Synopsys DesignWare pci core.
>>>>
>>>> Intel PCIe driver requires Upconfig support, fast training
>>>> sequence configuration and link speed change. So adding the
>>>> respective helper functions in the pcie DesignWare framework.
>>>> It also programs hardware autonomous speed during speed
>>>> configuration so defining it in pci_regs.h.
>>>>
>>>> +static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
>>>> +{
>>>> + u32 val;
>>>> +
>>>> + val = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCAP);
>>>> + lpp->max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);
>>>> + lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
>>>> +
>>>> + val = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCTL);
>>>> +
>>>> + val &= ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC);
>>>> + val |= (PCI_EXP_LNKSTA_SLC << 16) | PCI_EXP_LNKCTL_CCC |
>>>> + PCI_EXP_LNKCTL_RCB;
>>> PCI_EXP_LNKCTL_CCC is RW. But doesn't it depend on the components on
>>> both ends of the link? Do you know what device is at the other end?
>>> I would have assumed that you'd have to start with CCC==0, which
>>> should be most conservative, then set CCC=1 only if you know both ends
>>> have a common clock.
>> PCIe RC and endpoint device are having the common clock so set the CCC=1.
> How do you know what the endpoint device is? Is this driver only for
> a specific embedded configuration where the endpoint is always
> soldered down? There's no possibility of this RC being used with a
> connector?
>
> Shouldn't this be either discoverable or configurable via DT or
> something? pcie_aspm_configure_common_clock() seems to do something
> similar, but I can't really vouch for its correctness.
(sorry for the late reply, i am back today from sick leave)
I see pcie_aspm_configure_common_clock() is getting called during pcie
root bus bridge scanning and programming the CCC.
So, CCC configuration can be removed here in intel_pcie_link_setup().
Regards,
Dilip
>
> Bjorn
next prev parent reply other threads:[~2019-10-29 7:46 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-21 6:39 [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-10-21 6:39 ` [PATCH v4 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-10-21 11:19 ` Andrew Murray
2019-10-22 10:15 ` Dilip Kota
2019-10-24 20:31 ` Martin Blumenstingl
2019-10-29 7:53 ` Dilip Kota
2019-10-25 16:53 ` Rob Herring
2019-10-29 8:34 ` Dilip Kota
2019-10-31 10:51 ` Dilip Kota
2019-10-31 18:35 ` Rob Herring
2019-10-21 6:39 ` [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-10-21 8:29 ` Gustavo Pimentel
2019-10-21 10:44 ` Dilip Kota
2019-10-22 10:18 ` Dilip Kota
2019-10-22 11:44 ` andriy.shevchenko
2019-10-25 9:01 ` Andrew Murray
2019-10-29 6:14 ` Dilip Kota
2019-10-21 13:03 ` Andrew Murray
2019-10-22 9:04 ` Dilip Kota
2019-10-25 9:09 ` Andrew Murray
2019-10-29 8:59 ` Dilip Kota
2019-11-01 10:59 ` Andrew Murray
2019-11-04 9:34 ` Dilip Kota
2019-11-04 10:47 ` Andrew Murray
2019-10-21 17:17 ` Bjorn Helgaas
2019-10-22 9:07 ` Dilip Kota
2019-10-22 13:09 ` Bjorn Helgaas
2019-10-29 7:45 ` Dilip Kota [this message]
2019-10-24 6:57 ` kbuild test robot
2019-10-25 13:11 ` kbuild test robot
2019-10-25 13:11 ` [RFC PATCH] dwc: PCI: intel: intel_pcie_msi_init() can be static kbuild test robot
2019-10-21 6:39 ` [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link Dilip Kota
2019-10-21 8:40 ` Gustavo Pimentel
2019-10-21 10:34 ` Dilip Kota
2019-10-21 13:38 ` Andrew Murray
2019-10-21 17:18 ` Bjorn Helgaas
2019-10-22 9:27 ` Dilip Kota
2019-10-22 12:59 ` Bjorn Helgaas
2019-10-29 9:31 ` Dilip Kota
2019-10-30 22:14 ` Bjorn Helgaas
2019-10-30 23:31 ` Rafael J. Wysocki
2019-10-31 2:56 ` Bjorn Helgaas
2019-10-31 9:13 ` Rafael J. Wysocki
2019-10-31 13:01 ` Bjorn Helgaas
2019-10-31 10:47 ` Dilip Kota
2019-10-31 13:22 ` Bjorn Helgaas
2019-11-01 5:47 ` Dilip Kota
2019-11-01 11:30 ` Andrew Murray
2019-10-29 10:42 ` Rafael J. Wysocki
2019-10-29 12:36 ` Bjorn Helgaas
2019-10-22 9:20 ` Dilip Kota
2019-10-25 9:34 ` Andrew Murray
2019-10-29 9:51 ` Dilip Kota
2019-10-21 8:08 ` [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Gustavo Pimentel
2019-10-21 8:31 ` Dilip Kota
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