* [PATCH 1/3] arm64: dts: qcom: sdm845: Add first PCIe controller and PHY
2019-11-02 0:31 [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Bjorn Andersson
@ 2019-11-02 0:31 ` Bjorn Andersson
2019-11-02 0:31 ` [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller Bjorn Andersson
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2019-11-02 0:31 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
Add the GEN2 PCIe controller and PHY found on SDM845.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 104 +++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index ddb1f23c936f..b93537b7a59f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1364,6 +1364,110 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie0: pci@1c00000 {
+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
+ reg = <0 0x01c00000 0 0x2000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu";
+
+ iommus = <&apps_smmu 0x1c10 0xf>;
+ iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
+ <0x100 &apps_smmu 0x1c11 0x1>,
+ <0x200 &apps_smmu 0x1c12 0x1>,
+ <0x300 &apps_smmu 0x1c13 0x1>,
+ <0x400 &apps_smmu 0x1c14 0x1>,
+ <0x500 &apps_smmu 0x1c15 0x1>,
+ <0x600 &apps_smmu 0x1c16 0x1>,
+ <0x700 &apps_smmu 0x1c17 0x1>,
+ <0x800 &apps_smmu 0x1c18 0x1>,
+ <0x900 &apps_smmu 0x1c19 0x1>,
+ <0xa00 &apps_smmu 0x1c1a 0x1>,
+ <0xb00 &apps_smmu 0x1c1b 0x1>,
+ <0xc00 &apps_smmu 0x1c1c 0x1>,
+ <0xd00 &apps_smmu 0x1c1d 0x1>,
+ <0xe00 &apps_smmu 0x1c1e 0x1>,
+ <0xf00 &apps_smmu 0x1c1f 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ phys = <&pcie0_lane>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sdm845-qmp-pcie-phy";
+ reg = <0 0x01c06000 0 0x18c>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_CLK>,
+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie0_lane: lanes@1c06200 {
+ reg = <0 0x01c06200 0 0x128>,
+ <0 0x01c06400 0 0x1fc>,
+ <0 0x01c06800 0 0x218>,
+ <0 0x01c06600 0 0x70>;
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #phy-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+ };
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller
2019-11-02 0:31 [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Bjorn Andersson
2019-11-02 0:31 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add first PCIe controller and PHY Bjorn Andersson
@ 2019-11-02 0:31 ` Bjorn Andersson
2019-11-06 13:53 ` Georgi Djakov
2019-11-02 0:31 ` [PATCH 3/3] arm64: dts: qcom: db845c: Enable PCIe controllers Bjorn Andersson
2019-11-03 8:27 ` [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Vinod Koul
3 siblings, 1 reply; 7+ messages in thread
From: Bjorn Andersson @ 2019-11-02 0:31 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
Add the second PCIe controller and the associated QHP PHY found on
SDM845.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b93537b7a59f..0cdcc8d6d223 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1468,6 +1468,117 @@
};
};
+ pcie1: pci@1c08000 {
+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
+ reg = <0 0x01c08000 0 0x2000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ref",
+ "tbu";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ iommus = <&apps_smmu 0x1c00 0xf>;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
+ <0x200 &apps_smmu 0x1c02 0x1>,
+ <0x300 &apps_smmu 0x1c03 0x1>,
+ <0x400 &apps_smmu 0x1c04 0x1>,
+ <0x500 &apps_smmu 0x1c05 0x1>,
+ <0x600 &apps_smmu 0x1c06 0x1>,
+ <0x700 &apps_smmu 0x1c07 0x1>,
+ <0x800 &apps_smmu 0x1c08 0x1>,
+ <0x900 &apps_smmu 0x1c09 0x1>,
+ <0xa00 &apps_smmu 0x1c0a 0x1>,
+ <0xb00 &apps_smmu 0x1c0b 0x1>,
+ <0xc00 &apps_smmu 0x1c0c 0x1>,
+ <0xd00 &apps_smmu 0x1c0d 0x1>,
+ <0xe00 &apps_smmu 0x1c0e 0x1>,
+ <0xf00 &apps_smmu 0x1c0f 0x1>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>;
+ interconnect-names = "pcie-mem";
+
+ phys = <&pcie1_lane>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c0a000 {
+ compatible = "qcom,sdm845-qhp-pcie-phy";
+ reg = <0 0x01c0a000 0 0x800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie1_lane: lanes@1c06200 {
+ reg = <0 0x01c0a800 0 0x800>,
+ <0 0x01c0a800 0 0x800>,
+ <0 0x01c0b800 0 0x400>;
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #phy-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+ };
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller
2019-11-02 0:31 ` [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller Bjorn Andersson
@ 2019-11-06 13:53 ` Georgi Djakov
2019-11-06 19:15 ` Bjorn Andersson
0 siblings, 1 reply; 7+ messages in thread
From: Georgi Djakov @ 2019-11-06 13:53 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
Hi Bjorn,
On 2.11.19 г. 2:31 ч., Bjorn Andersson wrote:
> Add the second PCIe controller and the associated QHP PHY found on
> SDM845.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index b93537b7a59f..0cdcc8d6d223 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1468,6 +1468,117 @@
> };
> };
>
> + pcie1: pci@1c08000 {
> + compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
> + reg = <0 0x01c08000 0 0x2000>,
> + <0 0x40000000 0 0xf1d>,
> + <0 0x40000f20 0 0xa8>,
> + <0 0x40100000 0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "config";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_1_CLKREF_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> + clock-names = "pipe",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ref",
> + "tbu";
> +
> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + iommus = <&apps_smmu 0x1c00 0xf>;
> + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
> + <0x100 &apps_smmu 0x1c01 0x1>,
> + <0x200 &apps_smmu 0x1c02 0x1>,
> + <0x300 &apps_smmu 0x1c03 0x1>,
> + <0x400 &apps_smmu 0x1c04 0x1>,
> + <0x500 &apps_smmu 0x1c05 0x1>,
> + <0x600 &apps_smmu 0x1c06 0x1>,
> + <0x700 &apps_smmu 0x1c07 0x1>,
> + <0x800 &apps_smmu 0x1c08 0x1>,
> + <0x900 &apps_smmu 0x1c09 0x1>,
> + <0xa00 &apps_smmu 0x1c0a 0x1>,
> + <0xb00 &apps_smmu 0x1c0b 0x1>,
> + <0xc00 &apps_smmu 0x1c0c 0x1>,
> + <0xd00 &apps_smmu 0x1c0d 0x1>,
> + <0xe00 &apps_smmu 0x1c0e 0x1>,
> + <0xf00 &apps_smmu 0x1c0f 0x1>;
> +
> + resets = <&gcc GCC_PCIE_1_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_1_GDSC>;
> +
> + interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>;
> + interconnect-names = "pcie-mem";
Maybe leave this hunk out (although it looks good), until we conclude on these
refactoring patches [1].
Thanks,
Georgi
[1]
http://lore.kernel.org/r/1571278852-8023-1-git-send-email-daidavid1@codeaurora.org
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller
2019-11-06 13:53 ` Georgi Djakov
@ 2019-11-06 19:15 ` Bjorn Andersson
0 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2019-11-06 19:15 UTC (permalink / raw)
To: Georgi Djakov
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
On Wed 06 Nov 05:53 PST 2019, Georgi Djakov wrote:
> Hi Bjorn,
>
> On 2.11.19 ??. 2:31 ??., Bjorn Andersson wrote:
> > Add the second PCIe controller and the associated QHP PHY found on
> > SDM845.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++
> > 1 file changed, 111 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index b93537b7a59f..0cdcc8d6d223 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -1468,6 +1468,117 @@
> > };
> > };
> >
> > + pcie1: pci@1c08000 {
> > + compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
> > + reg = <0 0x01c08000 0 0x2000>,
> > + <0 0x40000000 0 0xf1d>,
> > + <0 0x40000f20 0 0xa8>,
> > + <0 0x40100000 0 0x100000>;
> > + reg-names = "parf", "dbi", "elbi", "config";
> > + device_type = "pci";
> > + linux,pci-domain = <1>;
> > + bus-range = <0x00 0xff>;
> > + num-lanes = <1>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > +
> > + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> > +
> > + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "msi";
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> > +
> > + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> > + <&gcc GCC_PCIE_1_AUX_CLK>,
> > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> > + <&gcc GCC_PCIE_1_CLKREF_CLK>,
> > + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> > + clock-names = "pipe",
> > + "aux",
> > + "cfg",
> > + "bus_master",
> > + "bus_slave",
> > + "slave_q2a",
> > + "ref",
> > + "tbu";
> > +
> > + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + iommus = <&apps_smmu 0x1c00 0xf>;
> > + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
> > + <0x100 &apps_smmu 0x1c01 0x1>,
> > + <0x200 &apps_smmu 0x1c02 0x1>,
> > + <0x300 &apps_smmu 0x1c03 0x1>,
> > + <0x400 &apps_smmu 0x1c04 0x1>,
> > + <0x500 &apps_smmu 0x1c05 0x1>,
> > + <0x600 &apps_smmu 0x1c06 0x1>,
> > + <0x700 &apps_smmu 0x1c07 0x1>,
> > + <0x800 &apps_smmu 0x1c08 0x1>,
> > + <0x900 &apps_smmu 0x1c09 0x1>,
> > + <0xa00 &apps_smmu 0x1c0a 0x1>,
> > + <0xb00 &apps_smmu 0x1c0b 0x1>,
> > + <0xc00 &apps_smmu 0x1c0c 0x1>,
> > + <0xd00 &apps_smmu 0x1c0d 0x1>,
> > + <0xe00 &apps_smmu 0x1c0e 0x1>,
> > + <0xf00 &apps_smmu 0x1c0f 0x1>;
> > +
> > + resets = <&gcc GCC_PCIE_1_BCR>;
> > + reset-names = "pci";
> > +
> > + power-domains = <&gcc PCIE_1_GDSC>;
> > +
> > + interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>;
> > + interconnect-names = "pcie-mem";
>
> Maybe leave this hunk out (although it looks good), until we conclude on these
> refactoring patches [1].
>
Yes that makes sense and it's not necessary for it to be functional,
will drop it for now.
Regards,
Bjorn
> Thanks,
> Georgi
>
> [1]
> http://lore.kernel.org/r/1571278852-8023-1-git-send-email-daidavid1@codeaurora.org
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: db845c: Enable PCIe controllers
2019-11-02 0:31 [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Bjorn Andersson
2019-11-02 0:31 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add first PCIe controller and PHY Bjorn Andersson
2019-11-02 0:31 ` [PATCH 2/3] arm64: dts: qcom: sdm845: Add second PCIe PHY and controller Bjorn Andersson
@ 2019-11-02 0:31 ` Bjorn Andersson
2019-11-03 8:27 ` [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Vinod Koul
3 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2019-11-02 0:31 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree, linux-kernel
Enable the two PCIe controllers found on the Dragonboard845c.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index f5a85caff1a3..c314b5d55796 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -340,6 +340,39 @@
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
};
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+
+ vddpe-3v3-supply = <&pcie0_3p3v_dual>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+};
+
+&pcie0_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
+&pcie1 {
+ status = "okay";
+ perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+};
+
+&pcie1_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
&pm8998_gpio {
vol_up_pin_a: vol-up-active {
pins = "gpio6";
@@ -382,6 +415,31 @@
};
&tlmm {
+ pcie0_default_state: pcie0-default {
+ clkreq {
+ pins = "gpio36";
+ function = "pci_e0";
+ bias-pull-up;
+ };
+
+ reset-n {
+ pins = "gpio35";
+ function = "gpio";
+
+ drive-strength = <2>;
+ output-low;
+ bias-pull-down;
+ };
+
+ wake-n {
+ pins = "gpio37";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
pcie0_pwren_state: pcie0-pwren {
pins = "gpio90";
function = "gpio";
@@ -390,6 +448,39 @@
bias-disable;
};
+ pcie1_default_state: pcie1-default {
+ perst-n {
+ pins = "gpio102";
+ function = "gpio";
+
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ clkreq {
+ pins = "gpio103";
+ function = "pci_e1";
+ bias-pull-up;
+ };
+
+ wake-n {
+ pins = "gpio11";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ reset-n {
+ pins = "gpio75";
+ function = "gpio";
+
+ drive-strength = <16>;
+ bias-pull-up;
+ output-high;
+ };
+ };
+
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes
2019-11-02 0:31 [PATCH 0/3] arm64: dts: qcom: sdm845: Add PCIe nodes Bjorn Andersson
` (2 preceding siblings ...)
2019-11-02 0:31 ` [PATCH 3/3] arm64: dts: qcom: db845c: Enable PCIe controllers Bjorn Andersson
@ 2019-11-03 8:27 ` Vinod Koul
3 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2019-11-03 8:27 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
On 01-11-19, 17:31, Bjorn Andersson wrote:
> Add PCIe controller and PHY nodes for SDM845 and enable them for the
> Dragonboard 845c.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
>
> The two series' that adding the PHY drivers and controller support can be found
> here:
> https://lore.kernel.org/linux-arm-msm/20191102001628.4090861-1-bjorn.andersson@linaro.org/T/#m6a892f4d6a8eefdd2c16b29b1cebb0023c69eac0
> https://lore.kernel.org/linux-arm-msm/20191102002721.4091180-1-bjorn.andersson@linaro.org/T/#m42ca469f4b23d534000a4b45a55d9739edbebdc4
>
> Bjorn Andersson (3):
> arm64: dts: qcom: sdm845: Add first PCIe controller and PHY
> arm64: dts: qcom: sdm845: Add second PCIe PHY and controller
> arm64: dts: qcom: db845c: Enable PCIe controllers
>
> arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 91 +++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 215 +++++++++++++++++++++
> 2 files changed, 306 insertions(+)
>
> --
> 2.23.0
--
~Vinod
^ permalink raw reply [flat|nested] 7+ messages in thread