[PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Dmitry Osipenko]

UART clock is divided using divisor values from DLM/DLL registers when
enable-bit is unset in clk register and clk's divider configuration isn't
taken onto account in this case. This doesn't cause any problems, but
let's add a check for the divider's enable-bit state, for consistency.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---

Changelog:

v2: In the comment to v1 Peter De Schrijver pointed out that UART's DLM/DLL
    registers configuration is used when enable bit is unset, thus the
    commit's title and message are changed accordingly.

 drivers/clk/tegra/clk-divider.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index e76731fb7d69..f33c19045386 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
 	int div, mul;
 	u64 rate = parent_rate;
 
-	reg = readl_relaxed(divider->reg) >> divider->shift;
-	div = reg & div_mask(divider);
+	reg = readl_relaxed(divider->reg);
+
+	if ((divider->flags & TEGRA_DIVIDER_UART) &&
+	    !(reg & PERIPH_CLK_UART_DIV_ENB))
+		return rate;
+
+	div = (reg >> divider->shift) & div_mask(divider);
 
 	mul = get_mul(divider);
 	div += mul;
-- 
2.23.0

Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Stephen Boyd]

Quoting Dmitry Osipenko (2019-10-29 17:48:13)
> UART clock is divided using divisor values from DLM/DLL registers when
> enable-bit is unset in clk register and clk's divider configuration isn't
> taken onto account in this case. This doesn't cause any problems, but
> let's add a check for the divider's enable-bit state, for consistency.
> 
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---

Is this going to be picked up or should I just apply atop the tegra PR?

Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Dmitry Osipenko]

14.11.2019 02:03, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2019-10-29 17:48:13)
>> UART clock is divided using divisor values from DLM/DLL registers when
>> enable-bit is unset in clk register and clk's divider configuration isn't
>> taken onto account in this case. This doesn't cause any problems, but
>> let's add a check for the divider's enable-bit state, for consistency.
>>
>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
> 
> Is this going to be picked up or should I just apply atop the tegra PR?

Looks like this patch missed the Tegra's PR by accident.

Stephen, I assume it will be easier if you could apply this patch atop.
The patch doesn't have any dependencies on any other patches, so it's
fine to apply it separately. Thanks in advance!

Thierry, please let us know if you have any objections.

Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Thierry Reding]

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On Thu, Nov 14, 2019 at 02:29:51PM +0300, Dmitry Osipenko wrote:
> 14.11.2019 02:03, Stephen Boyd пишет:
> > Quoting Dmitry Osipenko (2019-10-29 17:48:13)
> >> UART clock is divided using divisor values from DLM/DLL registers when
> >> enable-bit is unset in clk register and clk's divider configuration isn't
> >> taken onto account in this case. This doesn't cause any problems, but
> >> let's add a check for the divider's enable-bit state, for consistency.
> >>
> >> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >> ---
> > 
> > Is this going to be picked up or should I just apply atop the tegra PR?
> 
> Looks like this patch missed the Tegra's PR by accident.
> 
> Stephen, I assume it will be easier if you could apply this patch atop.
> The patch doesn't have any dependencies on any other patches, so it's
> fine to apply it separately. Thanks in advance!
> 
> Thierry, please let us know if you have any objections.

It's not so much that I missed to pick this up. It's just that it didn't
make it in time. This was posted just a couple of days before v5.4-rc6
and I had already finalized the branches at that point. Given that this
doesn't fix any actual issues it didn't seem worth to force it in at
that point.

That said, I don't have any objections if Stephen wants to pick this up
on top of the pull requests.

Thierry

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Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Dmitry Osipenko]

14.11.2019 14:56, Thierry Reding пишет:
> On Thu, Nov 14, 2019 at 02:29:51PM +0300, Dmitry Osipenko wrote:
>> 14.11.2019 02:03, Stephen Boyd пишет:
>>> Quoting Dmitry Osipenko (2019-10-29 17:48:13)
>>>> UART clock is divided using divisor values from DLM/DLL registers when
>>>> enable-bit is unset in clk register and clk's divider configuration isn't
>>>> taken onto account in this case. This doesn't cause any problems, but
>>>> let's add a check for the divider's enable-bit state, for consistency.
>>>>
>>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>
>>> Is this going to be picked up or should I just apply atop the tegra PR?
>>
>> Looks like this patch missed the Tegra's PR by accident.
>>
>> Stephen, I assume it will be easier if you could apply this patch atop.
>> The patch doesn't have any dependencies on any other patches, so it's
>> fine to apply it separately. Thanks in advance!
>>
>> Thierry, please let us know if you have any objections.
> 
> It's not so much that I missed to pick this up. It's just that it didn't
> make it in time. This was posted just a couple of days before v5.4-rc6
> and I had already finalized the branches at that point. Given that this
> doesn't fix any actual issues it didn't seem worth to force it in at
> that point.
> 
> That said, I don't have any objections if Stephen wants to pick this up
> on top of the pull requests.

Thanks!

Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Stephen Boyd]

Quoting Dmitry Osipenko (2019-11-14 04:10:51)
> > 
> > It's not so much that I missed to pick this up. It's just that it didn't
> > make it in time. This was posted just a couple of days before v5.4-rc6
> > and I had already finalized the branches at that point. Given that this
> > doesn't fix any actual issues it didn't seem worth to force it in at
> > that point.
> > 
> > That said, I don't have any objections if Stephen wants to pick this up
> > on top of the pull requests.
> 
> Thanks!

I'm fine to wait for it to come through a pull request next time. I just
wanted to know what to do with this patch in my queue.

Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

[Thierry Reding]

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On Wed, Oct 30, 2019 at 03:48:13AM +0300, Dmitry Osipenko wrote:
> UART clock is divided using divisor values from DLM/DLL registers when
> enable-bit is unset in clk register and clk's divider configuration isn't
> taken onto account in this case. This doesn't cause any problems, but
> let's add a check for the divider's enable-bit state, for consistency.
> 
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> 
> Changelog:
> 
> v2: In the comment to v1 Peter De Schrijver pointed out that UART's DLM/DLL
>     registers configuration is used when enable bit is unset, thus the
>     commit's title and message are changed accordingly.
> 
>  drivers/clk/tegra/clk-divider.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)

Stephen, feel free to apply this on top of the Tegra pull requests:

Acked-by: Thierry Reding <treding@nvidia.com>

> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index e76731fb7d69..f33c19045386 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
>  	int div, mul;
>  	u64 rate = parent_rate;
>  
> -	reg = readl_relaxed(divider->reg) >> divider->shift;
> -	div = reg & div_mask(divider);
> +	reg = readl_relaxed(divider->reg);
> +
> +	if ((divider->flags & TEGRA_DIVIDER_UART) &&
> +	    !(reg & PERIPH_CLK_UART_DIV_ENB))
> +		return rate;
> +
> +	div = (reg >> divider->shift) & div_mask(divider);
>  
>  	mul = get_mul(divider);
>  	div += mul;
> -- 
> 2.23.0
> 

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